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公开(公告)号：US20220068872A1
公开(公告)日：2022-03-03
申请号：US17030380
申请日：2020-09-24
发明人： Chia-Fu Hsu , Kai-Ming Yang , Pu-Ju Lin , Cheng-Ta Ko
IPC分类号： H01L23/00
摘要： A fabrication method of an electronic device bonding structure includes the following steps. A first electronic component including a first conductive bonding portion is provided. A second electronic component including a second conductive bonding portion is provided. A first organic polymer layer is formed on the first conductive bonding portion. A second organic polymer layer is formed on the second conductive bonding portion. Bonding is performed on the first electronic component and the second electronic component through the first conductive bonding portion and the second conductive bonding portion, such that the first electronic component and the second electronic component are electrically connected. The first organic polymer layer and the second organic polymer layer diffuse into the first conductive bonding portion and the second conductive bonding portion after the bonding. An electronic device bonding structure is also provided.
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公开(公告)号：US20220061157A1
公开(公告)日：2022-02-24
申请号：US17022128
申请日：2020-09-16
发明人： Kai-Ming YANG , Chen-Hao LIN , Bo-Cheng LIN
摘要： A wiring board includes a photosensitive insulating layer and a first wiring layer. The photosensitive insulating layer has a hole, a first surface and a second surface opposite to each other. The hole has a first end opening formed in the first surface, a second end opening formed in the second surface, an axis, and a sidewall surrounding the axis. Part of the sidewall extends toward the axis to form at least one annular flange. The first wiring layer is disposed on the first surface and includes a first pad, in which the hole exposes the first pad. There is at least one recessed cavity between the annular flange and the first pad. The minimum width of the annular flange is smaller than the maximum width of the recessed cavity.
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公开(公告)号：US20210398925A1
公开(公告)日：2021-12-23
申请号：US17463559
申请日：2021-09-01
摘要： A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.
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公开(公告)号：US11166387B2
公开(公告)日：2021-11-02
申请号：US16847688
申请日：2020-04-14
发明人： Kai-Ming Yang , Chen-Hao Lin , Pu-Ju Lin
摘要： A wiring board including a build-up circuit layer, a patterned conductive layer, first and second adhesion promoting material layers and first and second solder mask layers is provided. The build-up circuit layer has a first surface and a second surface opposite thereto. The patterned conductive layer is disposed on the second surface. The first adhesion promoting material layer is disposed on the first surface and includes at least one first opening. The second adhesion promoting material layer is disposed on the second surface and the patterned conductive layer, and includes at least one second opening. The first solder mask layer is disposed on the first adhesion promoting material layer and includes at least one third opening provided corresponding to the first opening. The second solder mask layer is disposed on the second adhesion promoting material layer and includes at least one fourth opening provided corresponding to the second opening.
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公开(公告)号：US20210296291A1
公开(公告)日：2021-09-23
申请号：US16846429
申请日：2020-04-13
发明人： Pu-Ju Lin , Chi-Hai Kuo , Kai-Ming Yang , Cheng-Ta Ko
IPC分类号： H01L25/075 , H01L33/62 , H01L33/52 , H01L33/00
摘要： A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit layer have been formed on the carrier. A flat structure layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and covers the flat structure layer and a portion of the first dielectric layer. A second patterned circuit layer is formed on the second dielectric layer. The second patterned circuit layer includes a plurality of pads. An orthographic projection of the flat structure layer on the carrier overlaps orthographic projections of the pads on the carrier. A plurality of chips are disposed on the pads. A molding compound is formed to cover the second dielectric layer and encapsulate the chips and the pads.
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公开(公告)号：US20210282277A1
公开(公告)日：2021-09-09
申请号：US17315357
申请日：2021-05-10
发明人： Wei-Ti Lin , Chun-Hsien Chien , Fu-Yang Chen
摘要： A circuit carrier board includes a first substrate and a second substrate bonding to the first substrate. The first substrate includes a first circuit layer connecting to a plurality of conductive structure. The conductive structures connect to electronic elements. The second substrate contacts the first circuit layer. The second substrate includes a plurality of stacked dielectric layers, and a plurality of second circuit layers are disposed in the dielectric layers. The bottommost layer of the second circuit layers is exposed outside of the dielectric layers, and the topmost layer of the second circuit layers is electrically connected to the first circuit layer. The conductive structure includes a pad and a conductive via. The pad electrically connects to the first circuit layer. A linewidth of the first circuit layer is smaller than a linewidth of the second circuit layer. A manufacturing method of the circuit carrier board is also provided.
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公开(公告)号：US20210242123A1
公开(公告)日：2021-08-05
申请号：US17234826
申请日：2021-04-20
发明人： Chien-Chen LIN
IPC分类号： H01L23/498 , H01L21/48 , H05K1/11
摘要： A method of manufacturing circuit board structure includes forming a sacrificial layer having first openings on a substrate; forming a metal layer on the sacrificial layer; forming a patterned photoresist layer having second openings over the sacrificial layer, in which the second openings are connected to the first openings and expose a portion of the metal layer; forming a first circuit layer filling the second openings and the first openings; forming a first dielectric layer over the sacrificial layer and covering the metal layer, in which the first dielectric layer has third openings exposing the first circuit layer; forming a second circuit layer filling the third openings and covering a portion of the first dielectric layer; removing the substrate to expose the sacrificial layer, a portion of the metal layer and a portion of the first circuit layer; and removing the sacrificial layer and the metal layer.
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公开(公告)号：US20210202407A1
公开(公告)日：2021-07-01
申请号：US16729488
申请日：2019-12-30
摘要： A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.
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公开(公告)号：US20210202394A1
公开(公告)日：2021-07-01
申请号：US17200892
申请日：2021-03-14
发明人： Yi LIN , Chun-Ming CHIU , Hung-Chih LEE , Chang-Fu CHEN
IPC分类号： H01L23/538 , H01L23/00 , H01L25/065 , H01L21/48
摘要： A package structure includes a first substrate, a second substrate, a plurality of dies, a plurality of first conductive elements, and a plurality of second conductive elements. The first substrate has a recessed region. The second substrate is disposed in the recessed region and protrudes from the first substrate. The dies are disposed on the first substrate and the second substrate, such that the second substrate is disposed between the first substrate and the dies. The first conductive elements are disposed between the dies and the first substrate. The dies are electrically connected with the first substrate through the first conductive elements. The second conductive elements are disposed between the dies and the second substrate. The dies are electrically connected with the second substrate through the second conductive elements.
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公开(公告)号：US20210195761A1
公开(公告)日：2021-06-24
申请号：US17194323
申请日：2021-03-08
发明人： Kai-Ming YANG , Chen-Hao LIN , Wang-Hsiang TSAI , Cheng-Ta KO
IPC分类号： H05K3/40 , H01L21/768 , H01L21/48 , H05K1/11 , H05K1/18 , H05K1/14 , H01L23/14 , H01L23/15 , H01L23/498 , H01L23/36 , H01L23/538 , H05K3/46 , H01L23/00 , H01L21/683
摘要： A package structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a chip, a circuit layer structure, and an insulating protective layer. The composite layer of the non-conductor inorganic material and the organic material is disposed on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the sealant, and the chip has electrode pads. The circuit layer structure is formed on the sealant and the chip. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protective layer has openings, so as to expose parts of the surface of the circuit layer structure in the openings.
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