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公开(公告)号：US12056062B2
公开(公告)日：2024-08-06
申请号：US17759973
申请日：2020-12-02
Applicant: ARM LIMITED
CPC classification number: G06F12/1458 , G06F9/3005 , G06F9/35
Abstract: Apparatus comprises a processor to execute program instructions stored at respective memory addresses, processing of the program instructions being constrained by a prevailing capability defining at least access permissions to a set of one or more memory addresses; the processor comprising: control flow change handling circuitry to perform a control flow change operation, the control flow change operation defining a control flow change target address indicating the address of a program instruction for execution after the control flow change operation; and capability generating circuitry to determine, in dependence on the control flow change target address, an address at which capability access permissions data is stored; the capability generating circuitry being configured to retrieve the capability access permissions data and to generate a capability for use as a next prevailing capability in dependence upon at least the capability access permissions data.
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公开(公告)号：US20240193101A1
公开(公告)日：2024-06-13
申请号：US18556468
申请日：2022-02-17
Applicant: Arm Limited
IPC: G06F12/14
CPC classification number: G06F12/1458
Abstract: A technique is provided for constraining access to memory using capabilities. An apparatus is provided that has processing circuitry for performing operations during which access request to memory are generated, wherein the processing circuitry is arranged to generate memory addresses for the access requests using capabilities that provide a pointer value and associated constraining information. The apparatus also provides capability generation circuitry, that is responsive to the processing circuitry executing a capability generating instruction that identifies a location in a literal pool of the memory, to retrieve a literal value from the location in the literal pool, and to produce a generated capability in which the pointer value of the generated capability is determined from the literal value. The constraining information of the generated capability is selected from a limited set of options in dependence on information specified by the capability generating instruction. It has been found that such an approach provides a robust mechanism for generating capabilities, whilst reducing code size.
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公开(公告)号：US11907720B2
公开(公告)日：2024-02-20
申请号：US17759978
申请日：2020-11-26
Applicant: ARM LIMITED
Inventor： Bradley John Smith , Thomas Christopher Grocutt
IPC: G06F9/30
CPC classification number: G06F9/30123 , G06F9/3013 , G06F9/30043 , G06F9/30112 , G06F9/30189
Abstract: There is provided a data processing apparatus comprising a plurality of registers, each of the registers having data bits to store data and metadata bits to store metadata. Each of the registers is adapted to operate in a metadata mode in which the metadata bits and the data bits are valid, and a data mode in which the data bits are valid and the metadata bits are invalid. Mode bit storage circuitry indicates whether each of the registers is in the data mode or the metadata mode. Execution circuitry is responsive to a memory operation that is a store operation on one or more given registers.
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公开(公告)号：US11720356B2
公开(公告)日：2023-08-08
申请号：US17271373
申请日：2019-08-20
Applicant: Arm Limited
Inventor： Thomas Christopher Grocutt
CPC classification number: G06F9/30021 , G06F9/30094 , G06F9/355
Abstract: An apparatus comprises an instruction decoder to decode instructions, processing circuitry to perform data processing in response to the instructions decoded by the instruction decoder, and memory attribute checking circuitry to check whether a memory access request issued by the processing circuitry satisfies access permissions specified in a plurality of memory attribute entries. Each memory attribute entry specifies access permissions for a corresponding address region of variable size within an address space. In response to a range checking instruction specifying address identifying parameters for identifying a first address and a second address, the instruction decoder controls the processing circuitry to set, in at least one software-accessible storage location, a status value indicative of whether the first address and the second address correspond to the same memory attribute entry.
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公开(公告)号：US11561882B2
公开(公告)日：2023-01-24
申请号：US16332130
申请日：2017-08-09
Applicant: ARM LIMITED
Inventor： François Christopher Jacques Botman , Thomas Christopher Grocutt , John Michael Horley , Michael John Williams , Michael John Gibbs
Abstract: An apparatus and method are provided for generating and processing a trace stream indicative of instruction execution by processing circuitry. An apparatus has an input interface for receiving instruction execution information from the processing circuitry indicative of a sequence of instructions executed by the processing circuitry, and trace generation circuitry for generating from the instruction execution information a trace stream comprising a plurality of trace elements indicative of execution by the processing circuitry of instruction flow changing instructions within the sequence. The sequence may include a branch behaviour setting instruction that indicates an identified instruction within the sequence, where execution of the branch behaviour setting instruction enables a branch behaviour to be associated with the identified instruction that causes the processing circuitry to branch to a target address identified by the branch behaviour setting instruction when the identified instruction is encountered in the sequence. The trace generation circuitry is further arranged to generate, from the instruction execution information, a trace element indicative of execution behaviour of the branch behaviour setting instruction, and a trace element to indicate that the branch behaviour has been triggered on encountering the identified instruction within the sequence. This enables a very efficient form of trace stream to be used even in situations where the instruction sequence executed by the processing circuitry includes such branch behaviour setting instructions.
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Patent Agency Ranking
46.发明授权公开(公告)号：US11294787B2
公开(公告)日：2022-04-05
申请号：US16321503
申请日：2017-08-10
Applicant: ARM LIMITED
Inventor： François Christopher Jacques Botman , Thomas Christopher Grocutt , John Michael Horley , Michael John Williams
Abstract: An apparatus and method are provided to control assertion of a trigger signal to processing circuitry. The apparatus has evaluation circuitry to receive program instruction execution information indicative of a program instruction executed by the processing circuitry, which is arranged to perform an evaluation operation to determine with reference to evaluation information whether the program instruction execution information indicates presence of a trigger condition. Trigger signal generation circuitry is used to assert a trigger signal to the processing circuitry in dependence on whether the trigger condition is determined to be present. Further, filter circuitry is arranged to receive event information indicative of at least one event occurring within the processing circuitry, and is arranged to determine with reference to filter control information and that event information whether a qualifying condition is present. The filter circuitry is arranged, on determining that the qualifying condition is not present, to prevent the presence of the trigger condition being notified to the trigger signal generation circuitry. This allows the monitoring of particular program instruction execution behaviour to be qualified so that the processing circuitry is only notified if in addition a qualifying event is determined to be present.
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公开(公告)号：US11126714B2
公开(公告)日：2021-09-21
申请号：US16149297
申请日：2018-10-02
Applicant: Arm Limited
Inventor： Alastair David Reid , Dominic Phillip Mulligan , Milosch Meriac , Matthias Lothar Boettcher , Nathan Yong Seng Chong , Ian Michael Caulfield , Peter Richard Greenhalgh , Frederic Claude Marie Piry , Albin Pierrick Tonnerre , Thomas Christopher Grocutt , Yasuo Ishii
Abstract: A data processing apparatus comprises branch prediction circuitry adapted to store at least one branch prediction state entry in relation to a stream of instructions, input circuitry to receive at least one input to generate a new branch prediction state entry, wherein the at least one input comprises a plurality of bits; and coding circuitry adapted to perform an encoding operation to encode at least some of the plurality of bits based on a value associated with a current execution environment in which the stream of instructions is being executed. This guards against potential attacks which exploit the ability for branch prediction entries trained by one execution environment to be used by another execution environment as a basis for branch predictions.
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公开(公告)号：US11036502B2
公开(公告)日：2021-06-15
申请号：US16314936
申请日：2017-06-06
Applicant: ARM LIMITED
Inventor： Thomas Christopher Grocutt
Abstract: An apparatus and method are provided for performing a vector rearrangement operation as data elements are moved between memory and vector registers. The apparatus has processing circuitry for performing operations specified by a sequence of program instructions, and a set of vector registers, where each vector register is arranged to store a vector comprising a plurality of data elements. The processing circuitry includes access circuitry to move the data elements between memory and multiple vector registers of the set, and to perform a rearrangement operation as the data elements are moved so that the data elements are arranged in a first organisation in the memory and are arranged in a second, different, organisation in the vector registers. Decode circuitry is arranged to be responsive to a group of rearrangement instructions within the sequence of program instructions to produce control signals to control execution of each rearrangement instruction by the processing circuitry. Each rearrangement instruction in the group defines a data element access pattern that differs to the data element access pattern defined by each other rearrangement instruction in the group, and that causes the access circuitry to access more than one vector register amongst the multiple vector registers involved in the rearrangement operation. Through such an approach, the access circuitry performs the rearrangement operation as a result of the processing circuitry executing all of the rearrangement instructions in the group. The use of such a group of rearrangement instructions can enable an efficient performance of the rearrangement operation by reducing stalling within the apparatus that might otherwise occur if all of the required steps to be performed to implement the rearrangement operation were implemented in response to execution of a single instruction.
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公开(公告)号：US10782972B2
公开(公告)日：2020-09-22
申请号：US16079241
申请日：2017-03-17
Applicant: ARM LIMITED
Inventor： Thomas Christopher Grocutt
IPC: G06F9/30
Abstract: An apparatus comprises processing circuitry (4) and an instruction decoder (6) which supports vector instructions for which multiple lanes of processing are performed on respective data elements of a vector value. In response to a vector predication instruction, the instruction decoder (6) controls the processing circuitry (4) to set control information based on the outcome of a number of element comparison operations each for determining whether a corresponding element passes or fails a test condition. The control information controls processing of a predetermined number of subsequent vector instructions after the vector predication instruction. The predetermined number is hard-wired or identified by the vector predication instruction. For one of the subsequent vector instructions, an operation for a given portion of a given lane of vector processing is masked based on the outcome indicated by the control information for a corresponding data element.
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公开(公告)号：US10747536B2
公开(公告)日：2020-08-18
申请号：US16080736
申请日：2017-03-21
Applicant: ARM LIMITED
Inventor： Alasdair Grant , Thomas Christopher Grocutt , Simon John Craske
Abstract: A data processing system provides a loop-end instruction for use at the end of a program loop body specifying an address of a beginning instruction of said program loop body. Loop control circuitry (1000) serves to control repeated execution of the program loop body upon second and subsequent passes through the program loop body using loop control data provided by the loop-end instruction without requiring the loop-end instruction to be explicitly executed upon each pass.
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