公开(公告)号：US12170263B2

公开(公告)日：2024-12-17

申请号：US16585480

申请日：2019-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Skyler J. Saleh ,  Ruijin Wu ,  Milind S. Bhagavat ,  Rahul Agarwal

IPC: H01L23/00 ,  G06F8/41 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00 ,  H01L25/065 ,  H01L21/60

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In some embodiments, a method of manufacture includes a face-to-face process in which a first GPU chiplet and a second GPU chiplet are bonded to a temporary carrier wafer. A face surface of an active bridge chiplet is bonded to a face surface of the first and second GPU chiplets before mounting the GPU chiplets to a carrier substrate. In other embodiments, a method of manufacture includes a face-to-back process in which a face surface of an active bridge chiplet is bonded to a back surface of the first and second GPU chiplets.

公开(公告)号：US12086899B2

公开(公告)日：2024-09-10

申请号：US17032268

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anirudh R. Acharya ,  Ruijin Wu ,  Paul E. Ruggieri

IPC: G06T1/20 ,  G06F9/48 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/4893 ,  G06T1/60

Abstract: Systems and methods related to run-time selection of a render mode in which to execute command buffers with a graphics processing unit (GPU) of a device based on performance data corresponding to the device are provided. A user mode driver (UMD) or kernel mode driver (KMD) executed at a central processing unit (CPU) selects abinning mode based on whether performance data that includes sensor data or performance counter data indicates that an associated binning condition or override condition has been met. The UMD or the KMD causes pending command buffers to be patched to execute in the selected binning mode based on whether the binning mode is enabled or disabled.

公开(公告)号：US20240257435A1

公开(公告)日：2024-08-01

申请号：US18633166

申请日：2024-04-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Mika Tuomi ,  Kiia Kallio ,  Ruijin Wu ,  Anirudh R. Acharya ,  Vineet Goel

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/08

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T15/08

Abstract: A processing device and a method of tiled rendering of an image for display is provided. The processing device includes memory and a processor. The processor is configured to receive the image comprising one or more three dimensional (3D) objects, divide the image into tiles, execute coarse level tiling for the tiles of the image and execute fine level tiling for the tiles of the image. The processing device also includes same fixed function hardware used to execute the coarse level tiling and the fine level tiling. The processor is also configured to determine visibility information for a first one of the tiles. The visibility information is divided into draw call visibility information and triangle visibility information for each remaining tile of the image.

公开(公告)号：US12014527B2

公开(公告)日：2024-06-18

申请号：US17187625

申请日：2021-02-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Kiia Kallio ,  Mika Tuomi ,  Ruijin Wu ,  Anirudh R. Acharya

IPC: G06T9/00 ,  G06T3/40 ,  G06T17/10 ,  G06T17/20 ,  H03M7/30 ,  H03M7/42

CPC classification number: G06T9/001 ,  G06T3/40 ,  G06T17/10 ,  G06T17/20 ,  H03M7/42 ,  H03M7/6005 ,  H03M7/6011

Abstract: Methods, devices, and systems for compressing and decompressing a stream of indices associated with graphics primitives. A group of delta values is determined based on a group of indices of the stream of indices. The group of delta values is compared to delta values in a lookup table. The group of indices is compressed based on an entry in the lookup table if the group of delta values matches all delta values in the entry, otherwise, the group of indices is compressed based on variable-length encoding.

公开(公告)号：US11972518B2

公开(公告)日：2024-04-30

申请号：US17033259

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Mika Tuomi ,  Kiia Kallio ,  Ruijin Wu ,  Anirudh R. Acharya ,  Vineet Goel

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/08

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T15/08

Abstract: A processing device and a method of tiled rendering of an image for display is provided. The processing device includes memory and a processor. The processor is configured to receive the image comprising one or more three dimensional (3D) objects, divide the image into tiles, execute coarse level tiling for the tiles of the image and execute fine level tiling for the tiles of the image. The processing device also includes same fixed function hardware used to execute the coarse level tiling and the fine level tiling. The processor is also configured to determine visibility information for a first one of the tiles. The visibility information is divided into draw call visibility information and triangle visibility information for each remaining tile of the image.

公开(公告)号：US11900499B2

公开(公告)日：2024-02-13

申请号：US17028803

申请日：2020-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Anirudh Rajendra Acharya ,  Ruijin Wu ,  Alexander Fuad Ashkar ,  Harry J. Wise

IPC: G06T1/20 ,  G06F9/54 ,  G06F9/38 ,  G06T7/60

CPC classification number: G06T1/20 ,  G06F9/3836 ,  G06F9/544 ,  G06T7/60

Abstract: A technique for executing commands for an accelerated processing device is provided. The technique includes obtaining an iteration number and predication data from metadata for an iterative indirect command buffer; for each iteration indicated by the iteration number, performing commands of the iterative indirect command buffer as specified by the predication data; and ending processing of the iterative indirect command buffer in response to processing a number of iterations equal to the iteration number.

公开(公告)号：US11880924B2

公开(公告)日：2024-01-23

申请号：US17565394

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Ruijin Wu ,  Mika Tuomi ,  Paavo Sampo Ilmari Pessi ,  Anirudh R. Acharya

IPC: G06T15/00 ,  G06T1/20

CPC classification number: G06T15/005 ,  G06T1/20

Abstract: A method of tiled rendering is provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles and interleaving execution of same subpasses of multiple tiles of the frame. Interleaving execution of same subpasses of multiple tiles comprises executing a previously ordered first subpass of a second tile between execution of the previously ordered first subpass of a first tile and execution of a subsequently ordered second subpass of the first tile. The interleaving is performed, for example, by executing the plurality of subpasses in an order different from the order in which the commands to execute the plurality of subpasses are stored and issued. Alternatively, interleaving is performed by executing one or more subpasses as skip operations such that the plurality of subpasses are executed in the same order.

公开(公告)号：US20220319091A1

公开(公告)日：2022-10-06

申请号：US17562872

申请日：2021-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Mika Tuomi ,  Ruijin Wu ,  Anirudh R. Acharya

IPC: G06T15/00 ,  G06T15/40

Abstract: A method and apparatus of tile rendering of an image for a display in a computer system includes receiving the image in a graphics pipeline of the computer system, the image comprising one or more three dimensional (3D) objects. The image is divided into one or more tiles. A depth test is performed on the one or more tiles, and based upon the depth test, visibility information of the one or more tiles is binned.

公开(公告)号：US20210192827A1

公开(公告)日：2021-06-24

申请号：US16723969

申请日：2019-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Vineet Goel ,  Pazhani Pillai ,  Ruijin Wu ,  Christopher J. Brennan ,  Andrew S. Pomianowski

IPC: G06T15/00 ,  G06T1/60 ,  G06T1/20

Abstract: Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data, and writing a VRS rate feedback buffer based on the updated VRS data.

公开(公告)号：US10783694B2

公开(公告)日：2020-09-22

申请号：US15687108

申请日：2017-08-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Maxim V. Kazakov ,  Skyler J. Saleh ,  Ruijin Wu ,  Sagar Shankar Bhandare

IPC: G06T15/00 ,  G06T15/04 ,  G06T15/80 ,  G06T9/00 ,  G06T1/60 ,  G06T17/20

Abstract: A pipeline is configured to access a memory that stores a texture block and metadata that encodes compression parameters of the texture block and a residency status of the texture block. A processor requests access to the metadata in conjunction with requesting data in the texture block to perform a shading operation. The pipeline selectively returns the data in the texture block to the processor depending on whether the metadata indicates that the texture block is resident in the memory. A cache can also be included to store a copy of the metadata that encodes the compression parameters of the texture block. The residency status and the metadata stored in the cache can be modified in response to requests to access the metadata stored in the cache.