公开(公告)号：US07847605B2

公开(公告)日：2010-12-07

申请号：US12242114

申请日：2008-09-30

申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Albert M. Chu ,  John A. Fifield

发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Albert M. Chu ,  John A. Fifield

IPC分类号： H03L7/00

CPC分类号： H03K5/153

摘要： An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.

摘要翻译： 一种集成电路，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。 隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。 第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。 随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。 运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

公开(公告)号：US20090144689A1

公开(公告)日：2009-06-04

申请号：US11948308

申请日：2007-11-30

申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Albert M. Chu ,  John A. Fifield

发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  Albert M. Chu ,  John A. Fifield

IPC分类号： G06F17/50

CPC分类号： G06F17/5063 ,  G06F2217/78

摘要： A design structure for an integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.

摘要翻译： 一种用于集成电路的设计结构，其包括用于产生触发标志信号的至少一个隧道装置电压检测电路。 隧道装置电压检测电路包括接收电源电压并具有对应的相应的第一和第二内部节点输出电压的第一和第二分压器。 第一和第二分压器被配置为使得第一输出电压相对于电源电压是线性的，并且使得第二输出电压相对于电源电压是非线性的。 随着电源电压上升，第一和第二输出电压的曲线在特定电压下交叉。 运算放大器电路检测第一和第二输出电压何时相等，并且响应于此，输出指示电源电压达到一定水平的触发信号。

公开(公告)号：US20080169867A1

公开(公告)日：2008-07-17

申请号：US11851138

申请日：2007-09-06

申请人： Wagdi W. ABADEER ,  Albert M. Chu

发明人： Wagdi W. ABADEER ,  Albert M. Chu

IPC分类号： G05F1/10

CPC分类号： G05F1/56

摘要： A design structure that includes at least one tunneling device voltage reference circuit for use in low voltage applications is disclosed. The tunneling device voltage reference circuit includes a pair of voltage dividing device stacks, one having a linear voltage output and the other having a non-linear voltage output. A feedback circuit supplies a regulated voltage to each of the voltage dividing stacks so that the output voltages of the two device stacks equalize. Once the feedback circuit has locked, any one of the device stack output voltages and the regulated voltage may be used as a voltage reference.

摘要翻译： 公开了一种包括用于低电压应用的至少一个隧道装置电压参考电路的设计结构。 隧道装置电压基准电路包括一对分压装置堆叠，一个具有线性电压输出，另一个具有非线性电压输出。 反馈电路向每个分压堆提供调节电压，使得两个器件堆叠的输出电压相等。 一旦反馈电路被锁定，则可以将器件堆叠输出电压和调节电压中的任一个用作电压基准。

公开(公告)号：US06671218B2

公开(公告)日：2003-12-30

申请号：US10013963

申请日：2001-12-11

申请人： Paul Gutwin ,  Jonathan B. Ashbrook ,  Michael Bogaczyk ,  Albert M. Chu ,  Ezra Hall ,  Daryl Seitzer

发明人： Paul Gutwin ,  Jonathan B. Ashbrook ,  Michael Bogaczyk ,  Albert M. Chu ,  Ezra Hall ,  Daryl Seitzer

IPC分类号： G11C700

CPC分类号： G11C11/406 ,  G11C15/043

摘要： A system and method is disclosed for simultaneously searching and refreshing a memory array of a dynamic content addressable memory (DCAM). According to the disclosed invention, the information stored in a row of DCAM cells being refreshed is transferred from the memory array into sense amplifiers, during a read phase of a refresh operation. A search for a matching entry can then be performed, with respect to the information that is transferred to the sense amplifiers. To determine if there is a match, search information is simultaneously compared to the information that has been transferred to the sense amplifiers and to the information that is stored in other rows of DCAM cells of said memory array. Finally, the refresh of that row is completed by restoring the information from the sense amplifiers to that row of DCAM cells.

摘要翻译： 公开了用于同时搜索和刷新动态内容可寻址存储器（DCAM）的存储器阵列的系统和方法。 根据所公开的发明，在刷新操作的读取阶段期间，将刷新的存储在一行DCAM单元中的信息从存储器阵列传送到读出放大器。 然后可以对传输到感测放大器的信息执行匹配条目的搜索。 为了确定是否存在匹配，搜索信息同时被传送到读出放大器的信息和存储在所述存储器阵列的DCAM单元的其它行中的信息进行比较。 最后，通过将读出放大器的信息恢复到该行DCAM单元，来完成该行的刷新。

公开(公告)号：US06025744A

公开(公告)日：2000-02-15

申请号：US62415

申请日：1998-04-17

申请人： Allan R. Bertolet ,  Albert M. Chu ,  Frank D. Ferraiolo ,  Samuel K. Weinstein

发明人： Allan R. Bertolet ,  Albert M. Chu ,  Frank D. Ferraiolo ,  Samuel K. Weinstein

IPC分类号： H03H11/26 ,  H03K5/00 ,  H03K5/1252 ,  H03K5/13

CPC分类号： H03K5/133 ,  H03K5/1252 ,  H03K2005/00058 ,  H03K2005/00156

摘要： A glitch free delay line multiplexing technique is described that includes an intermediate multiplexing system and an output multiplexer. The intermediate multiplexing system receives signals from a plurality of delay units and outputs a subset of delay signals that includes the signal presently selected, the signal presently selected with an additional delay, and the signal presently selected with one less delay. The intermediate multiplexing system receives a control word from a select mechanism in a non-time critical manner. The output multiplexer receives the least significant bits of the control word and outputs the selected signal.

摘要翻译： 描述了一种无毛刺延迟线复用技术，其包括中间复用系统和输出多路复用器。 中间复用系统从多个延迟单元接收信号并输出​​包括当前选择的信号的延迟信号的子集，当前选择的信号是附加的延迟，以及当前用一个较小延迟选择的信号。 中间复用系统以非时间关键的方式从选择机制接收控制字。 输出多路复用器接收控制字的最低有效位并输出所选择的信号。

公开(公告)号：US4812688A

公开(公告)日：1989-03-14

申请号：US139551

申请日：1987-12-30

申请人： Albert M. Chu ,  William R. Griffin

发明人： Albert M. Chu ,  William R. Griffin

IPC分类号： H03H11/26 ,  H01L27/092 ,  H03K5/00 ,  H03K5/13 ,  H03K5/04 ,  H03K3/017 ,  H03K17/284 ,  H03K17/687

CPC分类号： H03K5/133 ,  H01L27/092 ,  H03K2005/00195 ,  H03K2005/00215

摘要： A signal delay circuit is provided which includes first and second circuits arranged parallel to each other, the first circuit having serially connected first and second transistors and the second circuit having a third transistor, and a fourth transistor connected from the common point between the first and second transistors to the second circuit, a signal is applied to one end of the parallelly arranged first and second circuits while the first, second and fourth transistors are turned on with the third transistor being turned off.