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41.发明授权Advanced modular cell placement system with iterative one dimensional preplacement optimization 失效先进的模块化放置系统，具有迭代一维预置位优化
公开(公告)号：US5892688A
公开(公告)日：1999-04-06
申请号：US672335
申请日：1996-06-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for providing an optimal preplacement of cells on a bounded surface of a semiconductor chip is disclosed herein. A percentage of the cells have predetermined interconnections with other cells. The system initially locates the cells on said surface, then computes coordinates for interconnected cells, determines a weight associated with each cell, and calculates a new cell coordinate for each cell based on the coordinates and weights from said determining step.
摘要翻译： 本文公开了一种用于在半导体芯片的有界表面上提供单元的最佳预置位的系统。 细胞的百分比具有与其他细胞的预定互连。 系统首先将单元定位在所述表面上，然后计算互连单元的坐标，确定与每个单元相关联的重量，并且基于来自所述确定步骤的坐标和权重来计算每个单元的新单元坐标。
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公开(公告)号：US5872718A
公开(公告)日：1999-02-16
申请号：US672535
申请日：1996-06-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for optimally locating cells on the surface of an integrated circuit chip is presented herein. The system comprises constructing a plurality of neighborhoods containing elements positionally related to one another; initially evaluating the lowest level of region hierarchy; iteratively developing a logical one-dimensional preplacement of elements on said surface; performing an affinity driven discrete preplacement optimization; evaluating whether a highest level of regional hierarchy has been attained; iteratively performing a dispersion driven spring system to levelize cell density and an unconstrained sinusoidal optimization; executing a density levelizing procedure; iteratively optimizing while controlling element densities; removing element overlap; iteratively optimizing for desired spacing between elements, adjusting element spacing, and permuting elements; locating elements on grid lines; and iteratively performing a functional sieve crystallization.
摘要翻译： 本文提供了用于在集成电路芯片的表面上最佳地定位单元的系统。 该系统包括构成包含彼此位置相关的元素的多个邻域; 初步评估区域层次的最低水平; 迭代地开发所述表面上的元件的逻辑一维预置位; 执行亲和力驱动的离散预置位优化; 评估是否实现了最高层次的区域层级; 迭代地执行色散驱动弹簧系统来平衡细胞密度和无约束正弦优化; 执行密度调整程序; 迭代优化，同时控制元件密度; 去除元件重叠; 迭代地优化元件之间的期望间隔，调整元件间距和排列元件; 在网格线上定位元素; 并迭代进行功能筛结晶。
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43.发明授权Advanced modular cell placement system with neighborhood system driven optimization 失效具有邻域系统驱动优化的高级模块化放置系统
公开(公告)号：US5812740A
公开(公告)日：1998-09-22
申请号：US674605
申请日：1996-06-28
CPC分类号： G06F17/5072 , Y10S706/921
摘要： A system for computing an affinity for relocating a cell on a surface of a semiconductor chip is disclosed herein. The cell is located within a region and belongs to a net of cells. The system initially computes a weight associated with all cells in the net. The sytem then sums the weights of all cells in the net containing the cell for all cells located inside the region and at positions greater than and less than edges of the region and computes the affinity for moving the cell to points on the surface greater than, equal to, and less than the current position of the cell based on the weight sums from said summing function. The computing function further comprises combining the affinities determined based on weight sums with other affinities. The summing function further comprises computing a relationship between the amount of rows and columns of regions on the semiconductor chip surface, and the affinity computation function comprises combining the relationship with the weight sums.
摘要翻译： 本文公开了一种用于计算在半导体芯片的表面上重新定位单元的亲和度的系统。 细胞位于一个区域内，属于细胞网。 系统最初计算与网中所有单元相关联的权重。 系统然后将位于该区域内部以及大于和小于该区域边缘的位置的所有单元格的网格中包含单元格的所有单元格的权重相加，并计算将单元格移动到表面上的点的亲和力大于， 基于来自所述求和函数的权重和，等于并小于小区的当前位置。 计算功能还包括将基于权重和确定的亲和力与其他亲和度组合。 求和功能还包括计算半导体芯片表面上的行数和列数之间的关系，并且亲和度计算功能包括将关系与权重和组合。
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44.发明授权
公开(公告)号：US5808899A
公开(公告)日：1998-09-15
申请号：US672235
申请日：1996-06-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for optimizing placement of a plurality of cells located on a surface of a semiconductor chip divided into regions by grid lines is disclosed herein. The system first increases the size associated with each cell by a fixed amount. The system then performs various density equalization routines to all cells, and locates cells having a size greater than a predetermined quantity and fixes those cells. Finally, the system executes a plurality of optimal cell movement routines to crystallize cell placement.
摘要翻译： 本文公开了一种用于优化位于通过网格线划分为区域的半导体芯片的表面上的多个单元的布置的系统。 系统首先将与每个单元相关联的大小增加固定的量。 然后，系统对所有单元执行各种密度均衡例程，并且定位具有大于预定量的大小的单元并且固定这些单元。 最后，系统执行多个最优的单元移动程序以结晶单元放置。
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公开(公告)号：US5742086A
公开(公告)日：1998-04-21
申请号：US517153
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L29/78 , H01L29/41
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译： 披露了几个发明。 公开了一种使用六角形电池的电池结构。 该体系结构不限于六角形细胞。 单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。 公开了多向非正交三层金属布线。 该架构可以与三向路由组合以用于特别有利的设计。 在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。 沿三个方向延伸的导体优选地以三个不同的层形成。 公开了一种使半导体器件中的导线长度最小化的方法。 公开了一种使半导体器件中的金属间电容最小化的方法。 公开了一种称为“三元器件”的新型器件。 公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。 公开了三角形运算放大器和三极管。 公开了三角形读出放大器。 公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。 公开了一种可编程可变驱动晶体管。 公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。
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46.发明授权System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errors 有权用于实现可变数量错误的可配置二进制Bose-Chaudhuri-Hocquenghem（BCH）编码器的通用多极的系统和方法公开(公告)号：US08527851B2
公开(公告)日：2013-09-03
申请号：US12221484
申请日：2008-08-04
IPC分类号： H03M13/00
CPC分类号： H03M13/152 , H03M13/6516
摘要： The present invention is a configurable binary BCH encoder having a variable number of errors. The encoder may implement a universal multipole block which may be configured for receiving an error number input, which may include a maximum error number limit for the encoder, and for calculating a plurality of error coefficients based on the error number input. The encoder may be further configured for receiving a plurality of information bits of an information word. The encoder may be further configured for transmitting/outputting a first (ex.—unmodified) subset of the information bits as an encoder output. The encoder may be further configured for calculating a plurality of parity bits based on a second subset of the information bits and the error coefficients. The encoder may be further configured for transmitting/outputting the calculated parity bits as part of the encoder output.
摘要翻译： 本发明是具有可变数量的错误的可配置二进制BCH编码器。 编码器可以实现通用多极块，其可以被配置为用于接收错误号输入，其可以包括编码器的最大误差数限制，以及用于基于错误数输入来计算多个误差系数。 编码器还可以被配置为用于接收信息字的多个信息位。 编码器还可以被配置为用于发送/输出信息比特的第一（未修改）子集作为编码器输出。 编码器还可以被配置为基于信息位的第二子集和误差系数来计算多个奇偶校验位。 编码器可以被进一步配置为发送/输出计算的奇偶校验位作为编码器输出的一部分。
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公开(公告)号：US07882406B2
公开(公告)日：2011-02-01
申请号：US12118477
申请日：2008-05-09
IPC分类号： G11C29/00
CPC分类号： G01R31/31724 , G11C5/04 , G11C29/16 , G11C2029/0401
摘要： An apparatus comprising a processor and an internal memory. The processor may be configured to test an external memory using (i) a netlist and (ii) a testing program. The internal memory may be configured to store the testing program. The testing program may be downloadable to the internal memory independently from the storing of the netlist.
摘要翻译： 一种包括处理器和内部存储器的装置。 处理器可以被配置为使用（i）网表和（ii）测试程序来测试外部存储器。 内部存储器可以被配置为存储测试程序。 测试程序可以独立于存储网表而被下载到内部存储器。
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公开(公告)号：US20090133003A1
公开(公告)日：2009-05-21
申请号：US11944104
申请日：2007-11-21
IPC分类号： G06F9/45
摘要： A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to receive data from the processor related to commands to be executed during memory testing.
摘要翻译： 提供了一种用于测试电子存储器件中的多个存储器位置的存储器测试系统。 该系统包括集成到能够接收和存储编译的存储器测试程序的电子存储器件中的可编程存储器件。 处理器与可编程存储器设备进行通信，以读取和执行存储在可编程存储器设备中的已编译测试程序的指令，并且命令解释器被配置为从存储器测试期间执行的命令接收来自处理器的数据。
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49.发明授权FIFO memory with single port memory modules for allowing simultaneous read and write operations 有权具有单端口存储器模块的FIFO存储器，用于允许同时的读写操作公开(公告)号：US07181563B2
公开(公告)日：2007-02-20
申请号：US10692664
申请日：2003-10-23
IPC分类号： G06F12/00
摘要： The present invention is directed to a FIFO memory with single port memory modules that may allow simultaneous read and write operations. In an exemplary aspect of the present invention, a method for employing a FIFO memory with single port memory modules of half capacity to perform simultaneous read and write operations includes the following steps: (a) providing a first single port memory module for an even address of a read or write operation; (b) providing a second single port memory module for an odd address of a read or write operation; (c) alternating even address and odd address; and (d) when both a read request and a write request reach either the first single port memory module or the second single port memory module at a clock cycle, fulfilling the read request at the current clock cycle and fulfilling the write request at the next clock cycle.
摘要翻译： 本发明涉及具有单端口存储器模块的FIFO存储器，其可以允许同时的读和写操作。 在本发明的示例性方面，一种采用具有半容量的单端口存储器模块的FIFO存储器来执行同时读和写操作的方法包括以下步骤：（a）提供用于偶数地址的第一单端口存储器模块 的读或写操作; （b）提供用于读或写操作的奇数地址的第二单端口存储器模块; （c）交替地址和奇地址; 和（d）当读请求和写请求都在时钟周期到达第一单端口存储器模块或第二单端口存储器模块时，在当前时钟周期满足读请求并在下一个时刻满足写请求 时钟周期。
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50.发明授权公开(公告)号：US07096413B2
公开(公告)日：2006-08-22
申请号：US10299270
申请日：2002-11-19
CPC分类号： H03M13/6505 , H03M13/27 , H03M13/2957 , H03M13/6566
摘要： A decoder for access data stored in n memories comprises a function matrix containing addresses of the memory locations at unique coordinates. A decomposer sorts addresses from coordinate locations of first and second m×n matrices, such that each row contains no more than one address from the same memory. Positional apparatus stores entries in third and fourth m×n matrices identifying coordinates of addresses in the function matrix such that each entry in the third matrix is at coordinates that matches corresponding coordinates in the first matrix, and each entry in the fourth matrix is at coordinates that matches corresponding coordinates in the second matrix. The decoder is responsive to entries in the matrices for accessing data in parallel from the memories.
摘要翻译： 用于存储在n个存储器中的访问数据的解码器包括在唯一坐标处包含存储器位置的地址的函数矩阵。 分解器从第一和第二m×n矩阵的坐标位置排序地址，使得每行包含来自同一存储器的不超过一个地址。 位置装置存储识别功能矩阵中地址的坐标的第三和第四m×n矩阵中的条目，使得第三矩阵中的每个条目在与第一矩阵中的对应坐标匹配的坐标处，并且第四矩阵中的每个条目在匹配的坐标处 第二个矩阵中的对应坐标。 解码器响应于矩阵中的条目，用于从存储器并行访问数据。
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