公开(公告)号：US5973376A

公开(公告)日：1999-10-26

申请号：US517406

申请日：1995-08-21

申请人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

发明人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

IPC分类号： G06F17/50 ,  G11C5/02 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L27/108 ,  H01L27/11 ,  H01L27/118 ,  H01L29/06 ,  H03K19/0944 ,  H03K19/0948 ,  H01L31/352 ,  H01L23/52 ,  H01L29/78

CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G11C5/025 ,  G11C5/063 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0922 ,  H01L27/108 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807 ,  H03K19/09441 ,  H03K19/0948 ,  H01L29/0657 ,  H01L2924/0002

摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.

摘要翻译： 披露了几个发明。 公开了一种使用六角形电池的电池结构。 该体系结构不限于六角形细胞。 单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。 公开了多向非正交三层金属布线。 该架构可以与三向路由组合以用于特别有利的设计。 在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。 沿三个方向延伸的导体优选地以三个不同的层形成。 公开了一种使半导体器件中的导线长度最小化的方法。 公开了一种使半导体器件中的金属间电容最小化的方法。 公开了一种称为“三元器件”的新型器件。 公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。 公开了三角形运算放大器和三极管。 公开了三角形读出放大器。 公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。 公开了一种可编程可变驱动晶体管。 公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

公开(公告)号：US5963975A

公开(公告)日：1999-10-05

申请号：US932042

申请日：1997-09-17

申请人： Douglas B. Boyle ,  James S. Koford ,  Edwin R. Jones ,  Ranko Scepanovic ,  Michael D. Rostoker

发明人： Douglas B. Boyle ,  James S. Koford ,  Edwin R. Jones ,  Ranko Scepanovic ,  Michael D. Rostoker

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0817

摘要： The capacity of a cache memory is substantially reduced over that required for a multi-chip distributed shared memory (DSM) implementation to enable the cache memory, a main memory, a processor and requisite logic and control circuitry to fit on a single integrated circuit chip. The increased cache miss rate created by the reduced cache memory capacity is compensated for by the reduced cache miss resolution period resulting from integrating the main memory and processor on the single chip. The reduced cache miss resolution period enables the processor clock rate to be substantially increased, so that a processor having a simple functionality such as a reduced instruction set computer (RISC) processor can be utilized and still provide the required processing speed. The RISC processor is substantially smaller than a more complicated processor that would be required to provide the same processing speed in a multi-chip DSM implementation, thereby enabling the RISC processor to fit on the chip with the other elements. A single-chip communications node that can be used in telecommunications networks other than DSM includes a memory controller for providing local and remote memory coherency, and a bidirectional interconnect unit that converts memory access instructions into memory access messages and vice-versa.

摘要翻译： 高速缓冲存储器的容量比多芯片分布式共享存储器（DSM）实现所需的容量大大减少，以使得高速缓冲存储器，主存储器，处理器和必需的逻辑和控制电路能够安装在单个集成电路芯片 。 由降低的高速缓存存储器容量创建的增加的高速缓存未命中率由通过在单个芯片上集成主存储器和处理器而减少的高速缓存未命中分辨率周期来补偿。 减小的高速缓存未命中分辨率周期使得处理器时钟速率能够显着增加，使得可以利用具有简单功能的处理器，诸如精简指令集计算机（RISC）处理器，并且仍然提供所需的处理速度。 RISC处理器远小于在多芯片DSM实现中提供相同处理速度所需的更复杂的处理器，从而使RISC处理器能够与其他元件相配合。 可以用于DSM以外的电信网络中的单芯片通信节点包括用于提供本地和远程存储器一致性的存储器控​​制器，以及将存储器访问指令转换为存储器访问消息的反向互连的双向互连单元。

公开(公告)号：US5903461A

公开(公告)日：1999-05-11

申请号：US862791

申请日：1997-05-23

申请人： Michael D. Rostoker ,  James S. Koford ,  Edwin R. Jones ,  Douglas B. Boyle ,  Ranko Scepanovic

发明人： Michael D. Rostoker ,  James S. Koford ,  Edwin R. Jones ,  Douglas B. Boyle ,  Ranko Scepanovic

IPC分类号： G06F17/50 ,  G06F19/00

CPC分类号： G06F17/5072

摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.

摘要翻译： 在用于生成用于集成电路芯片的优化的单元布置的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。 重组优化过程的结果以产生优化的细胞放置。 分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。 该系统可以应用于初始放置，布线，布局改进等问题。 处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。 或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。 处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。

公开(公告)号：US5872380A

公开(公告)日：1999-02-16

申请号：US517189

申请日：1995-08-21

申请人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valerity B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

发明人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valerity B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

IPC分类号： G06F17/50 ,  G11C5/02 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L27/108 ,  H01L27/11 ,  H01L27/118 ,  H01L29/06 ,  H03K19/0944 ,  H03K19/0948 ,  H01L27/10

CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G11C5/025 ,  G11C5/063 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0922 ,  H01L27/108 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807 ,  H03K19/09441 ,  H03K19/0948 ,  H01L29/0657 ,  H01L2924/0002

摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.

摘要翻译： 披露了几个发明。 公开了一种使用六角形电池的电池结构。 该体系结构不限于六角形细胞。 单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。 公开了多向非正交三层金属布线。 该架构可以与三向路由组合以用于特别有利的设计。 在三向布线布置中，用于互连集成电路的微电子单元的端子的电导体优选地在彼此成角度地移位60度的三个方向上延伸。 沿三个方向延伸的导体优选地以三个不同的层形成。 公开了一种使半导体器件中的导线长度最小化的方法。 公开了一种使半导体器件中的金属间电容最小化的方法。 公开了一种称为“三元器件”的新型器件。 公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。 公开了三角形运算放大器和三极管。 公开了三角形读出放大器。 公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。 公开了一种可编程可变驱动晶体管。 公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

公开(公告)号：US5822214A

公开(公告)日：1998-10-13

申请号：US517171

申请日：1995-08-21

申请人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriv B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

发明人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriv B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

IPC分类号： G06F17/50 ,  G11C5/02 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L27/108 ,  H01L27/11 ,  H01L27/118 ,  H01L29/06 ,  H03K19/0944 ,  H03K19/0948 ,  G06F15/60

CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G11C5/025 ,  G11C5/063 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0922 ,  H01L27/108 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807 ,  H03K19/09441 ,  H03K19/0948 ,  H01L29/0657 ,  H01L2924/0002

摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.

摘要翻译： 披露了几个发明。 公开了一种使用六角形电池的电池结构。 该体系结构不限于六角形细胞。 单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。 公开了多向非正交三层金属布线。 该架构可以与三向路由组合以用于特别有利的设计。 在三向布线布置中，用于互连集成电路的微电子单元的端子的电导体优选地在三个方向上彼此成角度地移位60度。 沿三个方向延伸的导体优选地形成为三个不同的层。 公开了一种使半导体器件中的导线长度最小化的方法。 公开了一种使半导体器件中的金属间电容最小化的方法。 公开了一种称为“三元器件”的新型器件。 公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。 公开了三角形运算放大器和三极管。 公开了三角形读出放大器。 公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。 公开了一种可编程可变驱动晶体管。 公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

公开(公告)号：US5811863A

公开(公告)日：1998-09-22

申请号：US517463

申请日：1995-08-21

申请人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashook K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

发明人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashook K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

IPC分类号： G06F17/50 ,  G11C5/02 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L27/108 ,  H01L27/11 ,  H01L27/118 ,  H01L29/06 ,  H03K19/0944 ,  H03K19/0948 ,  H01L29/78 ,  H01L29/41

CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G11C5/025 ,  G11C5/063 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0922 ,  H01L27/108 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807 ,  H03K19/09441 ,  H03K19/0948 ,  H01L29/0657 ,  H01L2924/0002

摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.

摘要翻译： 披露了几个发明。 公开了一种使用六角形电池的电池结构。 该体系结构不限于六角形细胞。 单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。 公开了多向非正交三层金属布线。 该架构可以与三向路由组合以用于特别有利的设计。 在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。 沿三个方向延伸的导体优选地以三个不同的层形成。 公开了一种使半导体器件中的导线长度最小化的方法。 公开了一种使半导体器件中的金属间电容最小化的方法。 公开了一种称为“三元器件”的新型器件。 公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。 公开了三角形运算放大器和三极管。 公开了三角形读出放大器。 公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。 公开了一种可编程可变驱动晶体管。 公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

公开(公告)号：US5801422A

公开(公告)日：1998-09-01

申请号：US517266

申请日：1995-08-21

申请人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

发明人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

IPC分类号： G06F17/50 ,  G11C5/02 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L27/108 ,  H01L27/11 ,  H01L27/118 ,  H01L29/06 ,  H03K19/0944 ,  H03K19/0948 ,  H01L29/78

CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G11C5/025 ,  G11C5/063 ,  H01L23/5222 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0922 ,  H01L27/108 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/11807 ,  H03K19/09441 ,  H03K19/0948 ,  H01L29/0657 ,  H01L2924/0002

摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.

摘要翻译： 披露了几个发明。 公开了一种使用六角形电池的电池结构。 该体系结构不限于六角形细胞。 单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。 公开了多向非正交三层金属布线。 该架构可以与三向路由组合以用于特别有利的设计。 在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。 沿三个方向延伸的导体优选地以三个不同的层形成。 公开了一种使半导体器件中的导线长度最小化的方法。 公开了一种使半导体器件中的金属间电容最小化的方法。 公开了一种称为“三元器件”的新型器件。 公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。 公开了三角形运算放大器和三极管。 公开了三角形读出放大器。 公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。 公开了一种可编程可变驱动晶体管。 公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

公开(公告)号：US5682322A

公开(公告)日：1997-10-28

申请号：US229949

申请日：1994-04-19

申请人： Douglas B. Boyle ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Michael D. Rostoker

发明人： Douglas B. Boyle ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Michael D. Rostoker

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： The fitness of a cell placement for an integrated circuit chip is optimized by relocating at least some of cells to new locations that provide lower interconnect congestion. For each cell, the centroid of the net of cells to which the cell is connected is computed. The cell is then moved toward the centroid by a distance that is equal to the distance from the current position of the cell to the centroid multiplied by a "chaos" factor .lambda.. The value of .lambda. is selected such that the cell relocation operations will cause the placement to converge toward an optimal configuration without chaotic diversion, but with a sufficiently high chaotic element to prevent the optimization operation from becoming stuck at local fitness maxima. The new cell locations can be modified to include the effects of cells in other locations, such as by incorporating a function of cell density gradient or force direction into the computation. This spreads out clumps of cells so that the density of cells is more uniform throughout the placement. The attraction between cells in the nets is balanced against repulsion caused by a high local cell density, providing an optimized tradeoff of wirelength, feasibility and congestion.

摘要翻译： 通过将至少一些单元重定位到提供较低互连拥塞的新位置来优化用于集成电路芯片的单元布局的适应性。 对于每个单元，计算连接单元的单元格网格的质心。 然后，电池向质心移动一个距离，该距离等于从电池的当前位置到质心乘以“混沌”因子λ的距离。 选择λ的值，使得单元重定位操作将导致放置朝向最佳配置收敛而没有混沌转移，但是具有足够高的混沌元素以防止优化操作变得卡在局部适应度最大值。 可以修改新的单元位置以将单元格的效果包括在其他位置，例如通过将单元密度梯度或力方向的函数合并到计算中。 这扩散了细胞团，使得细胞的密度在整个放置期间更均匀。 网络中的细胞之间的吸引力与由局部细胞密度较高引起的排斥平衡，从而提供了线长，可行性和拥塞的最优化折中。

公开(公告)号：US5636125A

公开(公告)日：1997-06-03

申请号：US559206

申请日：1995-11-13

申请人： Michael D. Rostoker ,  James S. Koford ,  Edwin R. Jones ,  Douglas B. Boyle ,  Ranko Scepanovic

发明人： Michael D. Rostoker ,  James S. Koford ,  Edwin R. Jones ,  Douglas B. Boyle ,  Ranko Scepanovic

IPC分类号： G06F17/50 ,  G06F19/00

CPC分类号： G06F17/5072

摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.

摘要翻译： 在用于产生用于集成电路芯片的优化的单元布局的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。 重组优化过程的结果以产生优化的细胞放置。 分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。 该系统可以应用于初始放置，布线，布局改进等问题。 处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。 或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。 处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。

公开(公告)号：US5631581A

公开(公告)日：1997-05-20

申请号：US567952

申请日：1995-12-06

申请人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

发明人： Michael D. Rostoker ,  James S. Koford ,  Ranko Scepanovic ,  Edwin R. Jones ,  Gobi R. Padmanahben ,  Ashok K. Kapoor ,  Valeriy B. Kudryavtsev ,  Alexander E. Andreev ,  Stanislav V. Aleshin ,  Alexander S. Podkolzin

IPC分类号： H01L27/02 ,  H01L27/118 ,  H03K19/08 ,  H03K17/093

CPC分类号： H01L27/11803 ,  H01L27/0207 ,  H03K19/08

摘要： A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a triangle, and includes an active area formed within the periphery. First and second terminals are formed in the active area adjacent to two vertices of the triangle respectively, and first to third gates are formed between the first and second terminals. The gates have contacts formed outside the active area adjacent to a side of the triangle between the two vertices. The power supply connections to the first and second terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor are selected for each device to provide a desired AND, NAND, OR or NOR function. A third terminal can be formed between two of the gates and used as an output terminal to provide an AND/OR logic function. The devices are interconnected using three direction routing based on hexagonal geometry.

摘要翻译： 微电子集成电路包括半导体衬底和形成在衬底上的多个微电子器件。 每个装置具有由三角形限定的周边，并且包括形成在周边内的有效区域。 第一和第二端子分别形成在与三角形的两个顶点相邻的有源区域中，并且在第一和第二端子之间形成第一至第三栅极。 门形成在与两个顶点之间的三角形的一侧相邻的有源区域的外侧。 为每个器件选择与第一和第二端子的电源连接，导电类型（NMOS或PMOS）以及上拉或下拉电阻的添加，以提供所需的AND，NAND，或或NOR 功能。 可以在两个栅极之间形成第三端子，并且用作输出端子以提供与/或逻辑功能。 这些设备使用基于六边形几何的三向路由进行互连。