公开(公告)号：US10963414B2

公开(公告)日：2021-03-30

申请号：US16287986

申请日：2019-02-27

Applicant: Amazon Technologies, Inc.

Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

IPC: G06F13/40 ,  G06F15/78 ,  G06F9/445 ,  G06F13/42

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

公开(公告)号：US10915486B1

公开(公告)日：2021-02-09

申请号：US15809622

申请日：2017-11-10

Applicant: Amazon Technologies, Inc.

Inventor： Asif Khan ,  Thomas A. Volpe ,  Marc John Brooker ,  Marc Stephen Olson ,  Norbert Paul Kusters ,  Mark Bradley Davis ,  Robert Michael Johnson

IPC: G06F13/42 ,  G11C15/00 ,  G06F11/10

Abstract: Server computers often include one or more input/output (I/O) devices for communicating with a network or directly attached storage device. The data transfer latency for request can be reduced by utilizing ingress data placement logic to bypass the processor of the I/O device. For example, host memory descriptors can be stored in a memory of the I/O device to facilitate placement of the requested data.

公开(公告)号：US10423438B2

公开(公告)日：2019-09-24

申请号：US15282282

申请日：2016-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Mark Bradley Davis ,  Robert Michael Johnson ,  Christopher Joseph Pettey ,  Asif Khan ,  Nafea Bshara

IPC: G06F9/455 ,  G06F9/50 ,  G06F15/76

Abstract: In a multi-tenant environment, separate virtual machines can be used for configuring and operating different subsets of programmable integrated circuits, such as a Field Programmable Gate Array (FPGA). The programmable integrated circuits can communicate directly with each other within a subset, but cannot communicate between subsets. Generally, all of the subsets of programmable ICs are within a same host server computer within the multi-tenant environment, and are sandboxed or otherwise isolated from each other so that multiple customers can share the resources of the host server computer without knowledge or interference with other customers.

公开(公告)号：US10353843B1

公开(公告)日：2019-07-16

申请号：US15946683

申请日：2018-04-05

Applicant: Amazon Technologies, Inc.

Inventor： Mark Bradley Davis ,  Asif Khan ,  Thomas A. Volpe ,  Robert Michael Johnson

IPC: G06F13/40 ,  G06F13/42

Abstract: A device can include one of more configurable packet processing pipelines to process a plurality of packets. Each configurable packet processing pipeline can include a plurality of packet processing components, wherein each packet processing component is configured to perform one or more packet processing operations for the device. The plurality of packet processing components are coupled to a packet processing interconnect, wherein each packet processing component is configured to route the packets through the packet processing interconnect for the one or more configurable packet processing pipelines.

公开(公告)号：US20190213155A1

公开(公告)日：2019-07-11

申请号：US16361007

申请日：2019-03-21

Applicant: Amazon Technologies, Inc.

Inventor： Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Christopher Joseph Pettey ,  Nafea Bshara ,  Erez Izenberg

IPC: G06F13/362 ,  G06F13/40 ,  G06F9/50

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

公开(公告)号：US10284460B1

公开(公告)日：2019-05-07

申请号：US14981013

申请日：2015-12-28

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Leonard Thomas Tracy ,  Thomas A. Volpe ,  Mark Bradley Davis ,  Mark Noel Kelly ,  Stephen Callaghan ,  Justin Oliver Pietsch ,  Edward Crabbe

IPC: H04L12/721 ,  H04L12/26

Abstract: Network packet tracing may be implemented on packet processors or other devices that perform packet processing. As network packets are received, a determination may be made as to whether tracing is enabled for the network packets. For those network packets with tracing enabled, trace information may be generated and the network packets modified to include the trace information such that forwarding decisions for the network packets ignore the trace information. Trace information indicate a packet processor as a location in a route traversed by the network packets and may include ingress and egress timestamps. Forwarding decisions may then be made and the network packets sent according to the forwarding decisions. Tracing may be enabled or disabled by packet processors for individual network packets. Trace information may also be truncated at a packet processor.

公开(公告)号：US10282330B2

公开(公告)日：2019-05-07

申请号：US15280624

申请日：2016-09-29

Applicant: Amazon Technologies, Inc.

Inventor： Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Christopher Joseph Pettey ,  Nafea Bshara ,  Erez Izenberg

IPC: G06F15/18 ,  G06F13/362 ,  G06F13/40 ,  G06F9/50

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

公开(公告)号：US10108572B1

公开(公告)日：2018-10-23

申请号：US15887779

申请日：2018-02-02

Applicant: Amazon Technologies, Inc.

Inventor： Robert Michael Johnson ,  Marc John Brooker ,  Marc Stephen Olson ,  Mark Bradley Davis ,  Norbert Paul Kusters

IPC: G06F3/00 ,  G06F13/38 ,  G06F11/30 ,  G06F3/06 ,  G06F11/14 ,  G06F13/42

Abstract: Server computers may include one or more input/output (I/O) adapter devices for communicating with a network and/or direct-attached device. The I/O adapter device may implement processes to manage write requests in a general and flexible manner. The I/O adapter device may also implement processes to manage write requests in a fast an efficient—that is, low latency—manner. Low latency write requests processes may include determining that a write packet for a write request can be processed without additional assistance from a processor, once a processor has initiated a memory access request to fetch write data and also generated protocol information for transmitting the write packet. The I/O adapter device may then process and transmit the write packet through an offload pipeline, without interrupting a processor.

公开(公告)号：US20180089132A1

公开(公告)日：2018-03-29

申请号：US15279232

申请日：2016-09-28

Applicant: Amazon Technologies, Inc.

Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F9/44505 ,  G06F13/4282 ,  G06F15/7867 ,  G06F15/7871

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

公开(公告)号：US20180088992A1

公开(公告)日：2018-03-29

申请号：US15279164

申请日：2016-09-28

Applicant: Amazon Technologies, Inc.

Inventor： Mark Bradley Davis ,  Asif Khan ,  Christopher Joseph Pettey ,  Erez Izenberg ,  Nafea Bshara

IPC: G06F9/50 ,  G06F13/40

CPC classification number: G06F9/5005 ,  G06F9/45558 ,  G06F9/5077 ,  G06F9/541 ,  G06F13/4068 ,  G06F2213/0038

Abstract: A multi-tenant environment is described with configurable hardware logic (e.g., a Field Programmable Gate Array (FPGA)) positioned on a host server computer. For communicating with the configurable hardware logic, an intermediate host integrated circuit (IC) is positioned between the configurable hardware logic and virtual machines executing on the host server computer. The host IC can include management functionality and mapping functionality to map requests between the configurable hardware logic and the virtual machines. Shared peripherals can be located either on the host IC or the configurable hardware logic. The host IC can apportion resources amongst the different configurable hardware logics to ensure that no one customer can over consume resources.