公开(公告)号：US06657376B1

公开(公告)日：2003-12-02

申请号：US09323557

申请日：1999-06-01

Applicant: Kanwal K. Raina ,  Ammar Derraa

Inventor： Kanwal K. Raina ,  Ammar Derraa

IPC: H01J162

CPC classification number: H01J1/3044 ,  H01J9/025

Abstract: In one aspect, an electron emission device comprises a substrate, and a first layer supported by the substrate. The first layer comprises a conductive material. The electron emission display device further comprises an electron emission tip electrically connected with the first layer, and a second layer electrically disposed between the first layer and the electron emission tip. The second layer comprises microcrystalline silicon. In another aspect, the invention encompasses a method of forming an electron emission device. A substrate is provided, and a conductive layer is formed over the substrate. A microcrystalline-silicon-containing layer is formed over the conductive layer, and a resistor layer is formed over the microcrystalline-silicon-containing layer. An emitter tip is formed over the resistor layer. In yet other aspects, the invention encompasses field emission display devices, and methods of forming field emission display devices.

Abstract translation: 一方面，电子发射器件包括衬底和由衬底支撑的第一层。 第一层包括导电材料。 电子发射显示装置还包括与第一层电连接的电子发射尖端，以及电气设置在第一层和电子发射尖端之间的第二层。 第二层包括微晶硅。 另一方面，本发明包括形成电子发射装置的方法。 提供衬底，并且在衬底上形成导电层。 在导电层上形成微晶硅层，在微晶硅层上形成电阻层。 发射极尖端形成在电阻层上。 在其它方面，本发明包括场发射显示装置，以及形成场致发射显示装置的方法。

公开(公告)号：US06650043B1

公开(公告)日：2003-11-18

申请号：US09358165

申请日：1999-07-20

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J102

CPC classification number: H01J29/02 ,  H01J31/127

Abstract: The disclosed multilayer conductor may be used in place of aluminum conductive lines in integrated circuits and field emission displays. The multilayer conductor includes a primary conductive line, preferably made from aluminum, and a protective line, preferably made from chromium. The protective line separates the aluminum from adjacent silicon-based layers.

Abstract translation: 所公开的多层导体可以用于集成电路和场致发射显示器中的铝导线。 多层导体包括优选由铝制成的初级导电线，以及优选由铬制成的保护线。 保护线将铝与相邻的硅基层分开。

公开(公告)号：US06600264B2

公开(公告)日：2003-07-29

申请号：US09942222

申请日：2001-08-29

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J1910

CPC classification number: H01J9/025

Abstract: A field emission array includes a plurality of pixels. Each pixel includes at least one resistor, at least one emitter tip overlying each resistor, and at least one substantially vertically oriented conductive line positioned laterally adjacent each resistor. The pixels may be arranged in substantially parallel lines. Adjacent pixels are separated and electrically isolated from one another by recessed areas located therebetween. Each conductive line is located within a recessed area. The conductive lines of a field emission array that includes lines of pixels may contact the resistors of each pixel of the corresponding line of pixels. Base portions of at least some of the emitter tips of the field emission array may overlie a portion of the conductive line that corresponds to the pixel of which such emitter tips are a part. Field emission displays that include such field emission arrays are also disclosed.

Abstract translation: 场致发射阵列包括多个像素。 每个像素包括至少一个电阻器，覆盖每个电阻器的至少一个发射极尖端以及横向邻近每个电阻器定位的至少一个基本垂直取向的导电线路。 像素可以以基本平行的线排列。 相邻的像素被分离并且通过位于其间的凹陷区域彼此电隔离。 每个导线位于凹陷区域内。 包括像素线的场发射阵列的导线可以接触相应像素线的每个像素的电阻。 场发射阵列的至少一些发射极尖端的基极部分可以覆盖导电线的对应于其发射极尖端为其一部分的像素的部分。 还公开了包括这种场致发射阵列的场致发射显示器。

公开(公告)号：US06548947B2

公开(公告)日：2003-04-15

申请号：US09879785

申请日：2001-06-12

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J702

CPC classification number: H01J9/025 ,  H01J3/022 ,  H01J2329/00

Abstract: A method for fabricating row lines over a field emission array in which two mask steps are used to define row lines and pixel openings through selected regions of each row line. A first mask may be employed in the removal of dielectric material and conductive material from between pixel rows and from substantially above each pixel of the field emission array. A second mask may be used in the removal of semiconductor material from between the adjacent rows of pixels. Alternatively, a first mask may be employed in the definition of row lines, while a second mask may be used in the formation of pixel openings. Field emission arrays having a semiconductive grid and a relatively thin passivation layer exposed between adjacent row lines are also disclosed.

Abstract translation: 一种用于在场发射阵列上制造行线的方法，其中使用两个掩模步骤来定义穿过每条行线的选定区域的行线和像素开口。 第一掩模可以用于从像素行之间以及从场发射阵列的每个像素的大致上方去除电介质材料和导电材料。 第二掩模可以用于从相邻行像素之间移除半导体材料。 或者，可以在行线的定义中采用第一掩模，而可以在形成像素开口中使用第二掩模。 还公开了具有在相邻行线之间暴露的半导电栅格和相对薄的钝化层的场致发射阵列。

公开(公告)号：US06406927B2

公开(公告)日：2002-06-18

申请号：US09944231

申请日：2001-08-30

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01L2100

CPC classification number: H01J9/025 ,  H01J3/022 ,  H01J2329/00

Abstract: A method for fabricating row lines over a field emission array employs only two mask steps to define row lines and pixel openings. A layer of conductive material is disposed over a substantially planarized surface of a grid of semiconductive material and a layer of passivation material is disposed over the layer of conductive material. Row lines and pixel openings may be formed through the passivation and conductive layers by use of a first mask. The row lines may be further defined by using a second mask to remove semiconductive material of the grid. Alternatively, a first mask may be used to fully define row lines from the layers of passivation, conductive, and semiconductive material, while a second mask may be used to define pixel openings through the layers of passivation and conductive material. Field emission arrays fabricated by such methods are also disclosed.

公开(公告)号：US06403390B2

公开(公告)日：2002-06-11

申请号：US09788984

申请日：2001-02-20

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01L2100

CPC classification number: H01J9/025

Abstract: A method of fabricating a field emission array to facilitate optimization of the size of grid openings. The method also minimizes the occurrence of electrical shorts between the cathode and anode grid of the field emission array. In the method of the present invention, a first layer of dielectric material is disposed over a substrate and emitter tips of the field emission array. A second layer is disposed over the first layer and subsequently planarized to expose regions of the first layer that are located above the emitter tips. Dielectric material of the first layer may be removed through openings of the second layer to expose a top portion of each of the emitter tips. The second layer is then substantially removed from the first layer. Planarization and removal of the second layer may reduce any conductive defects that extend through the first layer. A third layer, which comprises dielectric material, is disposed over the first layer. A fourth layer of grid material is disposed over the third layer, then planarized to expose dielectric material located over the emitter tips. The dielectric material exposed through the fourth layer is removed to define grid openings or apertures through the fourth layer. Dielectric material may also be removed through the grid openings to space the first and third layers apart from the emitter tips. Field emission arrays fabricated in accordance with the method of the present invention are also within the scope of the present invention.

Abstract translation: 一种制造场致发射阵列以便于优化栅极开口尺寸的方法。 该方法还使得场发射阵列的阴极和阳极栅极之间的电短路的发生最小化。 在本发明的方法中，介电材料的第一层设置在衬底上，并且发射阵列的发射极尖端。 第二层设置在第一层上并随后被平坦化以暴露位于发射极尖端上方的第一层的区域。 可以通过第二层的开口去除第一层的电介质材料，以露出每个发射极尖端的顶部。 然后基本上从第一层移除第二层。 平面化和去除第二层可以减少延伸穿过第一层的任何导电缺陷。 包括电介质材料的第三层设置在第一层上。 第四层栅格材料设置在第三层上，然后被平坦化以暴露位于发射极尖端上方的介电材料。 通过第四层暴露的电介质材料被去除以限定通过第四层的栅格开口或孔。 电介质材料也可以通过网格开口去除以使第一和第三层与发射极尖端分开。 根据本发明的方法制造的场发射阵列也在本发明的范围内。

公开(公告)号：US06276982B1

公开(公告)日：2001-08-21

申请号：US09626481

申请日：2000-07-26

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J902

CPC classification number: H01J9/025

Abstract: A method of fabricating a field emission array that employs a single mask to define the emitter tips thereof and their corresponding resistors. A layer of conductive material is disposed over a substrate of the field emission array. A plurality of substantially mutually parallel conductive lines is defined from the layer of conductive material. At least one layer of semiconductive material or conductive material is disposed over the conductive lines and over the regions of the substrate exposed between adjacent conductive lines. A mask material is disposed over the layer of semiconductive material or conductive material, substantially above each of the conductive lines. Portions of the layer of semiconductive material or conductive material exposed through the mask material may be removed to expose substantially longitudinal center portions of the conductive lines. Other portions of the layer of semiconductive material or conductive material may remain over peripheral lateral edges of the conductive lines. The mask material may be removed and the layer of semiconductive material or conductive material planarized. A mask is disposed over the field emission array and portions of the layer of semiconductive material or conductive material removed therethrough to define emitter tips and their corresponding resistors. The substantially longitudinal center portion of each of the conductive lines may be removed to electrically isolate adjacent columns of pixels of the field emission array from each other. Field emission arrays fabricated by the method of the present invention are also within the scope of the present invention.

Abstract translation: 一种制造场致发射阵列的方法，其使用单个掩模来限定其发射极尖端及其对应的电阻器。 导电材料层设置在场致发射阵列的衬底上。 多个基本相互平行的导电线由导电材料层限定。 至少一层半导体材料或导电材料设置在导电线之上和暴露在相邻导电线之间的衬底的区域之上。 掩模材料设置在半导体材料或导电材料层上，基本上在每条导电线上方。 通过掩模材料暴露的半导体材料或导电材料层的部分可以被去除以暴露导电线的基本上纵向的中心部分。 半导体材料或导电材料层的其它部分可以保留在导电线的外围横向边缘上。 可以去除掩模材料并将半导体材料或导电材料层平坦化。 掩模设置在场发射阵列之上，半导体材料或导电材料层的部分通过其去除以限定发射极尖端及其对应的电阻器。 每个导线的基本上纵向的中心部分可被去除以将场发射阵列的相邻列彼此电隔离。 通过本发明的方法制造的场发射阵列也在本发明的范围内。

公开(公告)号：US06271623B1

公开(公告)日：2001-08-07

申请号：US09651596

申请日：2000-08-30

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J102

CPC classification number: H01J9/025 ,  H01J3/022 ,  H01J2329/00

Abstract: A method of fabricating row lines over a field emission array. The method employs only two mask steps to define row lines and pixel openings through selected regions of each of the row lines. In accordance with the method of the present invention, a layer of conductive material is disposed over a substantially planarized surface of a grid of semiconductive material. A layer of passivation material is then disposed over the layer of conductive material. In one embodiment of the method, a first mask may be employed to remove passivation material and conductive material from between adjacent rows of pixels and from substantially above each of the pixels of the field emission array. A second mask is employed to remove semiconductive material from between the adjacent rows of pixels. In another embodiment of the method, a first mask is employed to facilitate removal of passivation material, conductive material, and semiconductive material from between adjacent rows of pixels of the field emission array. A second mask is employed to facilitate the removal of passivation material and conductive material from the desired areas of pixel openings. The present invention also includes field emission arrays having a semiconductive grid and a relatively thin passivation layer exposed between adjacent row lines.

Abstract translation: 一种在场发射阵列上制造行线的方法。 该方法仅采用两个掩模步骤来通过每条行线的选定区域来定义行线和像素开口。 根据本发明的方法，将导电材料层设置在半导体材料格栅的基本上平坦化的表面上。 然后将一层钝化材料设置在导电材料层上。 在该方法的一个实施例中，可以使用第一掩模来从相邻的像素行之间以及从场发射阵列的每个像素的大致上方去除钝化材料和导电材料。 采用第二掩模从相邻的像素行之间移除半导体材料。 在该方法的另一个实施例中，使用第一掩模以便于从场致发射阵列的相邻行像素之间移除钝化材料，导电材料和半导体材料。 使用第二掩模来促进从像素开口的期望区域去除钝化材料和导电材料。 本发明还包括具有半导电栅格的场发射阵列和暴露在相邻行线之间的相对薄的钝化层。

公开(公告)号：US06235545B1

公开(公告)日：2001-05-22

申请号：US09251262

申请日：1999-02-16

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01L2100

CPC classification number: H01J9/025 ,  H01J2201/30403

Abstract: In one aspect, the invention encompasses a method of treating the end portions of an array of substantially upright silicon-comprising structures. A substrate having a plurality of substantially upright silicon-comprising structures extending thereover is provided. The substantially upright silicon-comprising structures have base portions, and have end portions above the base portions. A masking layer is formed over the substrate to cover the base portions of the substantially upright silicon-comprising structures while leaving the end portions exposed. The end portions are then exposed to conditions which alter the end portions relative to the base portions. In another aspect, the invention encompasses a method of treating the ends of an array of silicon-comprising emitter structures. A substrate having a plurality of silicon-comprising emitter structures thereover is provided. The emitter structures have base portions and ends above the base portions. A layer of spin-on-glass is formed over the substrate. The layer of spin-on-glass covers the base portions of the emitter structures and leaves the ends exposed. The ends are then exposed to conditions which alter the ends relative to the base portions. In yet another aspect, the invention encompasses a cathode assembly which includes a plurality of silicon-comprising emitter structures projecting over a substrate. The emitter structures have base portions and ends above the base portions, and the ends comprise a different material than the base portions.

Abstract translation: 在一个方面，本发明包括一种处理基本上直立的含硅结构阵列的端部的方法。 提供了一种具有多个基本上直立的含硅结构延伸到其上的衬底。 基本上直立的含硅结构具有基部，并且在基部上方具有端部。 掩模层形成在衬底上以覆盖基本上直立的含硅结构的基部，同时使端部露出。 然后将端部暴露于相对于基部改变端部的条件。 在另一方面，本发明包括处理含硅发射体结构阵列的端部的方法。 提供了具有多个其上含硅的发射体结构的衬底。 发射极结构具有基部并且在基部上方结束。 在衬底上形成一层旋涂玻璃。 旋涂玻璃层覆盖发射器结构的基部并使端部露出。 然后将端部暴露于相对于基部改变端部的条件。 在另一方面，本发明包括阴极组件，其包括在衬底上突出的多个包含硅的发射器结构。 发射极结构具有基部和端部在基部之上，并且端部包括与基部不同的材料。

公开(公告)号：US06204077B1

公开(公告)日：2001-03-20

申请号：US09393672

申请日：1999-09-10

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01L2100

CPC classification number: H01J9/025 ,  H01J3/022 ,  H01J2329/00

Abstract: A method of fabricating row lines over a field emission array. The method employs only two mask steps to define row lines and pixel openings through selected regions of each of the row lines. In accordance with the method of the present invention, a layer of conductive material is disposed over a substantially planarized surface of a grid of semiconductive material. A layer of passivation material is then disposed over the layer of conductive material. In one embodiment of the method, a first mask may be employed to remove passivation material and conductive material from between adjacent rows of pixels and from substantially above each of the pixels of the field emission array. A second mask is employed to remove semiconductive material from between the adjacent rows of pixels. In another embodiment of the method, a first mask is employed to facilitate removal of passivation material, conductive material, and semiconductive material from between adjacent rows of pixels of the field emission array. A second mask is employed to facilitate the removal of passivation material and conductive material from the desired areas of pixel openings. The present invention also includes field emission arrays having a semiconductive grid and a relatively thin passivation layer exposed between adjacent row lines.