公开(公告)号：US20240135988A1

公开(公告)日：2024-04-25

申请号：US17971226

申请日：2022-10-20

Applicant: Arm Limited

Inventor： Vianney Antoine Choserot ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are related to a device having a storage node with a bitcell. The device may have a first stage that performs a first write based on an internal bitline signal, a first write wordline signal and a second write wordline signal. The first stage outputs the internal bitline signal. The device may have a second stage that receives the internal bitline signal and performs a second write of the internal bitline signal to the bitcell. The device may have a third stage with write wordline ports and write bitline ports. The third stage provides the internal bitline signal based on a selected write wordline signal from a write wordline port of the write wordline ports and based on a selected bitline signal based on a write bitline port of the write bitline ports.

公开(公告)号：US11901290B2

公开(公告)日：2024-02-13

申请号：US17149145

申请日：2021-01-14

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Andy Wangkun Chen

IPC: H01L23/528 ,  H01L21/8238 ,  H10B10/00 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L23/528 ,  H01L21/823871 ,  H01L23/5226 ,  H01L27/092 ,  H10B10/00 ,  H10B10/12

Abstract: Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The device may include multiple wordlines that are coupled to the multiple transistors. Also, one or more wordlines may be formed with frontside metal, and one or more other wordlines may be formed with buried metal.

公开(公告)号：US20230136348A1

公开(公告)日：2023-05-04

申请号：US17515258

申请日：2021-10-29

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Munish Kumar ,  Andy Wangkun Chen ,  Rajiv Kumar Sisodia

IPC: G11C7/06 ,  G11C5/06 ,  G11C7/10

Abstract: Various implementations described herein are directed to a device having memory control circuitry having global passgates and a read-write driver that provides a global read-write signal to the global passgates. The device may have sense amplifier circuitry with local-drivers and a sense amplifier driver that provides a sense amplifier enable signal to the local-drivers, wherein the local-drivers may include multiple buffers coupled to the sense amplifier driver in parallel.

公开(公告)号：US11624777B2

公开(公告)日：2023-04-11

申请号：US16857144

申请日：2020-04-23

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Pratik Ghanshambhai Satasia ,  Yew Keong Chong ,  Andy Wangkun Chen ,  Mouli Rajaram Chollangi

IPC: G06F30/3312 ,  G01R31/28 ,  G06F119/12

Abstract: Various implementations described herein are related to a method for constructing integrated circuitry and identifying input signal paths, internal signal paths and output signal paths associated with the integrated circuitry. The method may include generating a timing table for slew-load characterization of the input signal paths, the internal signal paths and the output signal paths. The method may include simulating corner points for the timing table, building diagonal points for the timing table based on the simulated corner points, and building remaining points for the timing table based on the simulated corner points and the diagonal points.

公开(公告)号：US20220319586A1

公开(公告)日：2022-10-06

申请号：US17223950

申请日：2021-04-06

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Ayush Kulshrestha ,  Munish Kumar

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.

公开(公告)号：US20220309225A1

公开(公告)日：2022-09-29

申请号：US17209903

申请日：2021-03-23

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Andy Wangkun Chen

IPC: G06F30/3953

Abstract: Various implementations described herein are directed to a method for identifying pre-routed metal lines in a higher layer of a multi-layered structure. The method may recognize gaps in the pre-routed metal lines of the higher layer, and also, the method may automatically fill the gaps with conductive stubs to modify the pre-routed metal lines in the higher layer as a continuous metal line with an extended length.

公开(公告)号：US20220246206A1

公开(公告)日：2022-08-04

申请号：US17162532

申请日：2021-01-29

Applicant: Arm Limited

Inventor： Mudit Bhargava ,  Rahul Mathur ,  Andy Wangkun Chen

IPC: G11C11/419 ,  G11C11/418

Abstract: According to one implementation of the present disclosure, an integrated circuit comprises a memory macro unit that includes an input/output (I/O) circuit block, where read/write circuitry of the I/O circuit block is apportioned on at least first and second tiers of the memory macro unit. In a particular implementation, read circuitry of the read/write circuitry is arranged on the first tier and write circuitry of the read/write circuitry is arranged on the second tier.

公开(公告)号：US11322197B1

公开(公告)日：2022-05-03

申请号：US17076540

申请日：2020-10-21

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Andy Wangkun Chen ,  Ayush Kulshrestha ,  Sony ,  Sriram Thyagarajan ,  Yew Keong Chong

IPC: G11C5/14 ,  G11C11/418

Abstract: Various implementations described herein are related to a device having wordline drivers coupled to a core array. The device may have backside power network with buried power rails. The device may have header logic coupled to power supply connections of the wordline drivers by way of the buried power rails, and the header logic may be used to power-gate the wordline drivers.

公开(公告)号：US11315628B1

公开(公告)日：2022-04-26

申请号：US17076305

申请日：2020-10-21

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Andy Wangkun Chen ,  Ayush Kulshrestha ,  Sony

IPC: G11C11/417 ,  H01L27/11

Abstract: Various implementations described herein are directed to a device having memory with a first array and a second array. The device may have power rails formed in frontside metal layers that supply core voltage to the memory. The power rails may include a first path routed through a first frontside metal layer to the first array of the memory, and the power rails may include a second path routed through the first frontside metal layer and a second frontside metal layer to the second array of the memory.

公开(公告)号：US20220077134A1

公开(公告)日：2022-03-10

申请号：US17017551

申请日：2020-09-10

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/48 ,  G06F30/392 ,  G06F30/3953

Abstract: Various implementations described herein refer to a device having logic circuitry with transistors and gate lines. The device may include a backside power network having buried supply rails with at least one buried supply rail having a continuity break. The transistors may be arranged in a cell architecture having an N-well break with the gate lines passing through the N-well break and the continuity break.