公开(公告)号：US20120094498A1

公开(公告)日：2012-04-19

申请号：US12904294

申请日：2010-10-14

申请人： Abhishek Dube ,  Eric Chad Toppin Harley ,  Richard John Murphy

发明人： Abhishek Dube ,  Eric Chad Toppin Harley ,  Richard John Murphy

IPC分类号： H01L21/306

CPC分类号： H01L21/3065

摘要： A method for reducing punch-through defects during semiconductor fabrication is disclosed. Various parameters such as partial pressure, total pressure, and temperature are manipulated to reduce punch-through defects, while still maintaining an acceptable etch rate. Some embodiments of the present invention also comprise the use of precursors, such as germane, to achieve faster etch rates with lower etch temperatures.

摘要翻译： 公开了一种用于在半导体制造期间减少穿通缺陷的方法。 操作各种参数，例如分压，总压力和温度，以减少穿通缺陷，同时仍然保持可接受的蚀刻速率。 本发明的一些实施方案还包括使用诸如锗烷之类的前体以更低的蚀刻温度实现更快的蚀刻速率。

公开(公告)号：US20110316044A1

公开(公告)日：2011-12-29

申请号：US12823163

申请日：2010-06-25

申请人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Jinghong Li ,  Dae-Gyu Park ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Jinghong Li ,  Dae-Gyu Park ,  Zhengmao Zhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer.

摘要翻译： 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底的上表面上的至少一个FET栅极堆叠。 所述至少一个FET栅极堆叠包括在所述至少一个FET栅极堆叠中的覆盖区域处位于所述半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且位于半导体衬底内的嵌入式应力元件。 每个嵌入式应力元件包括从底部到顶部的第一外延掺杂半导体材料的第一层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变;第二层 位于第一层顶部的第二外延掺杂半导体材料和位于第二层的上表面上的掺杂剂的Δ单层。 该结构还包括直接位于三角形单层的上表面上的金属半导体合金触点。

公开(公告)号：US20110193193A1

公开(公告)日：2011-08-11

申请号：US12704084

申请日：2010-02-11

申请人： Abhishek Dube ,  Subramanian S. Iyer ,  Babar Ali Khan ,  Oh-jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Chengwen Pei ,  Gerd Pfeiffer ,  Ravi M. Todi ,  Geng Wang

发明人： Abhishek Dube ,  Subramanian S. Iyer ,  Babar Ali Khan ,  Oh-jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Chengwen Pei ,  Gerd Pfeiffer ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L29/94 ,  H01L21/02

CPC分类号： H01L29/945 ,  H01L21/76229 ,  H01L21/84 ,  H01L29/66181

摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.

摘要翻译： 公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。 该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区域。 该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

公开(公告)号：US20070098902A1

公开(公告)日：2007-05-03

申请号：US11454538

申请日：2006-06-16

申请人： James Engstrom ,  Andrew Chadeayne ,  Peter Wolczanski ,  Abhishek Dube ,  Manish Sharma

发明人： James Engstrom ,  Andrew Chadeayne ,  Peter Wolczanski ,  Abhishek Dube ,  Manish Sharma

IPC分类号： B05D3/10

CPC分类号： B05D1/185 ,  B05D3/107 ,  B05D2202/40 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L51/0075 ,  H01L51/0595

摘要： Systems and methods for preparing inorganic-organic interfaces using transition metal coordination complexes and self-assembled monolayers as organic surfaces. In one embodiment, a silicon wafer supports a polycrystalline gold layer, optionally using an intermediate adhesionlayer such as Cr. The surface is reacted with the thiophene end of organic molecular species comprising a thiophene moiety to prepare self assembling monomers (SAMs). The functionalized end of the SAM is then reacted with metal-bearing species such as tetrakis(dimethylamido)titanium, Ti[N(CH3)2]4, (TDMAT) to provide a titanium nitride layer.

摘要翻译： 使用过渡金属配位络合物和自组装单层作为有机表面制备无机 - 有机界面的系统和方法。 在一个实施例中，硅晶片可以任选地使用诸如Cr的中间粘附层来支撑多晶金层。 表面与包含噻吩部分的有机分子物质的噻吩末端反应以制备自组装单体（SAM）。 然后将SAM的官能化端与含金属物质如四（二甲基氨基）钛，Ti [N（CH 3）2）4， / SUB>（TDMAT）以提供氮化钛层。