公开(公告)号：US08946033B2

公开(公告)日：2015-02-03

申请号：US13561352

申请日：2012-07-30

Applicant: Thomas N. Adam ,  Keith E. Fogel ,  Jinghong Li ,  Alexander Reznicek

Inventor： Thomas N. Adam ,  Keith E. Fogel ,  Jinghong Li ,  Alexander Reznicek

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/16 ,  H01L29/161 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795

Abstract: A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of the two or more fins are (100) surfaces and the longitudinal axes of the two or more fins aligned with a [100] direction; a gate dielectric layer on each fin of the two or more fins; an electrically conductive gate over the gate dielectric layer over the central region of each fin of the of two or more fins; and a merged source/drain comprising an a continuous layer of epitaxial semiconductor material on ends of each fin of the two or more fins, the ends on a same side of the conductive gate.

Abstract translation: 翅片finFET和其制造方法。 鳍状FET包括：在半导体衬底上的绝缘层的顶表面上的两个或多个单晶半导体鳍片，两个或更多鳍片的每个翅片具有位于第一和第二端部区域之间的中间区域和相对的两侧，顶表面 并且两个或更多个翅片的侧壁是（100）表面，并且两个或更多个翅片的纵向轴线与[100]方向对准; 在两个或更多个翅片的每个翅片上的栅介质层; 在两个或更多个翅片的每个翅片的中心区域上方的栅极电介质层上的导电栅极; 以及合并的源极/漏极，其包括在两个或更多个鳍片的每个鳍片的端部上的连续的外延半导体材料层，其端部位于导电栅极的同一侧。

公开(公告)号：US08035141B2

公开(公告)日：2011-10-11

申请号：US12607104

申请日：2009-10-28

Applicant: Kevin K. Chan ,  Abhishek Dube ,  Jinghong Li ,  Viorel Ontalus ,  Zhengmao Zhu

Inventor： Kevin K. Chan ,  Abhishek Dube ,  Jinghong Li ,  Viorel Ontalus ,  Zhengmao Zhu

IPC: H01L29/76

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  Y10S257/90 ,  Y10S257/902 ,  Y10S257/903

Abstract: A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.

Abstract translation: 公开了一种包括双层nFET嵌入式应力元件的半导体结构。 双层nFET嵌入式应力元件可以集成到任何CMOS工艺流程中。 双层nFET嵌入式应力元件包括具有不同于半导体衬底的晶格常数的晶格常数的第一外延半导体材料的免费第一层的植入物，并且在nFET栅极堆叠的器件沟道中施加拉伸应变 。 通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第一层由Si：C组成。 双层nFET嵌入式应力元件还包括具有比第一外延半导体材料更低的掺杂剂扩散阻力的第二外延半导体材料层。 通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第二层由硅组成。 双层nFET嵌入式应力元件的第二层仅包括注入的源极/漏极区域。

公开(公告)号：US08666518B2

公开(公告)日：2014-03-04

申请号：US13356712

申请日：2012-01-24

Applicant: Anthony J. Ticknor ,  Jinghong Li ,  Robert Lombaerde

Inventor： Anthony J. Ticknor ,  Jinghong Li ,  Robert Lombaerde

IPC: G05B11/01 ,  G05B15/00 ,  G05B15/02 ,  G05B23/02 ,  G06F11/00

CPC classification number: G05B23/0256

Abstract: A method, a system, and a computer program product for managing one or more electronic devices. Performance of an electronic device is monitored and presented to a user through a digital agent interface. The performance of the electronic device is controlled automatically by digital agent through the digital agent interface. The invention also enables automatic testing of the electronic device through the digital agent interface by setting up test configurations, activating test signals, and interpreting any error codes that may be generated.

Abstract translation: 一种用于管理一个或多个电子设备的方法，系统和计算机程序产品。 监视电子设备的性能并通过数字代理接口向用户呈现。 电子设备的性能由数字代理通过数字代理接口自动控制。 本发明还能够通过设置测试配置，激活测试信号和解释可能产生的任何错误代码，通过数字代理接口来自动测试电子设备。

公开(公告)号：US20130193492A1

公开(公告)日：2013-08-01

申请号：US13360823

申请日：2012-01-30

Applicant: THOMAS N. ADAM ,  Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Jinghong Li ,  Alexander Reznicek

Inventor： THOMAS N. ADAM ,  Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Jinghong Li ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L21/20

CPC classification number: H01L21/0245 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7848

Abstract: An improved silicon carbon film structure is disclosed. The film structure comprises multiple layers of silicon carbon and silicon. The multiple layers form stress film structures that have increased substitutional carbon content, and serve to induce stresses that improve carrier mobility for certain types of field effect transistors.

Abstract translation: 公开了一种改进的硅碳膜结构。 膜结构包括多层硅碳和硅。 多层形成具有增加的取代碳含量的应力膜结构，并且用于诱导改善某些类型的场效应晶体管的载流子迁移率的应力。

公开(公告)号：US20090099669A1

公开(公告)日：2009-04-16

申请号：US12248594

申请日：2008-10-09

Applicant: Anthony J. Ticknor ,  Jinghong Li ,  Robert Lombaerde

Inventor： Anthony J. Ticknor ,  Jinghong Li ,  Robert Lombaerde

IPC: G05B15/00

CPC classification number: G05B23/0256

Abstract: A method, a system, and a computer program product for managing one or more electronic devices. Performance of an electronic device is monitored and presented to a user through a digital agent interface. The performance of the electronic device is controlled automatically by digital agent through the digital agent interface. The invention also enables automatic testing of the electronic device through the digital agent interface by setting up test configurations, activating test signals, and interpreting any error codes that may be generated.

Abstract translation: 一种用于管理一个或多个电子设备的方法，系统和计算机程序产品。 监视电子设备的性能并通过数字代理接口向用户呈现。 电子设备的性能由数字代理通过数字代理接口自动控制。 本发明还能够通过设置测试配置，激活测试信号和解释可能产生的任何错误代码，通过数字代理接口来自动测试电子设备。

公开(公告)号：US20140027863A1

公开(公告)日：2014-01-30

申请号：US13561352

申请日：2012-07-30

Applicant: Thomas N. Adam ,  Keith E. Fogel ,  Jinghong Li ,  Alexander Reznicek

Inventor： Thomas N. Adam ,  Keith E. Fogel ,  Jinghong Li ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L29/16 ,  H01L29/161 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795

Abstract: A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of the two or more fins are (100) surfaces and the longitudinal axes of the two or more fins aligned with a [100] direction; a gate dielectric layer on each fin of the two or more fins; an electrically conductive gate over the gate dielectric layer over the central region of each fin of the of two or more fins; and a merged source/drain comprising an a continuous layer of epitaxial semiconductor material on ends of each fin of the two or more fins, the ends on a same side of the conductive gate.

Abstract translation: 翅片finFET和其制造方法。 鳍状FET包括：在半导体衬底上的绝缘层的顶表面上的两个或多个单晶半导体鳍片，两个或更多鳍片的每个翅片具有位于第一和第二端部区域之间的中间区域和相对的两侧，顶表面 并且两个或更多个翅片的侧壁是（100）表面，并且两个或更多个翅片的纵向轴线与[100]方向对准; 在两个或更多个翅片的每个翅片上的栅介质层; 在两个或更多个翅片的每个翅片的中心区域上方的栅极电介质层上的导电栅极; 以及合并的源极/漏极，其包括在两个或更多个鳍片的每个鳍片的端部上的连续的外延半导体材料层，其端部位于导电栅极的同一侧。

公开(公告)号：US08421191B2

公开(公告)日：2013-04-16

申请号：US13533499

申请日：2012-06-26

Applicant: Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

Inventor： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jinghong Li ,  Joseph S. Newbury ,  Viorel Ontalus ,  Dae-Gyu Park ,  Zhengmao Zhu

IPC: H01L31/117

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

Abstract: Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.

Abstract translation: 公开了包括位于半导体衬底上的至少一个FET栅叠层的半导体结构。 所述至少一个FET栅极堆叠包括位于半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 嵌入式应力元件位于至少一个FET栅极堆叠的相对侧并且位于半导体衬底内。 每个应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，以及第二外延掺杂半导体材料的上层。 至少一个单层的掺杂剂位于每个嵌入的应力元件的上层内。

公开(公告)号：US20110095343A1

公开(公告)日：2011-04-28

申请号：US12607104

申请日：2009-10-28

Applicant: Kevin K. Chan ,  Abhishek Dube ,  Jinghong Li ,  Viorel Ontalus ,  Zhengmao Zhu

Inventor： Kevin K. Chan ,  Abhishek Dube ,  Jinghong Li ,  Viorel Ontalus ,  Zhengmao Zhu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7834 ,  Y10S257/90 ,  Y10S257/902 ,  Y10S257/903

Abstract: A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.

Abstract translation: 公开了一种包括双层nFET嵌入式应力元件的半导体结构。 双层nFET嵌入式应力元件可以集成到任何CMOS工艺流程中。 双层nFET嵌入式应力元件包括具有不同于半导体衬底的晶格常数的晶格常数的第一外延半导体材料的免费第一层的植入物，并且在nFET栅极堆叠的器件沟道中施加拉伸应变 。 通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第一层由Si：C组成。 双层nFET嵌入式应力元件还包括具有比第一外延半导体材料更低的掺杂剂扩散阻力的第二外延半导体材料层。 通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第二层由硅组成。 双层nFET嵌入式应力元件的第二层仅包括注入的源极/漏极区域。

公开(公告)号：US20110062518A1

公开(公告)日：2011-03-17

申请号：US12561606

申请日：2009-09-17

Applicant: Kevin K. Chan ,  Thomas Safron Kanarsky ,  Jinghong Li ,  Christine Qiqing Ouyang ,  Dae-Gyu Park ,  Zhibin Ren ,  Xinhui Wang ,  Haizhou Yin

Inventor： Kevin K. Chan ,  Thomas Safron Kanarsky ,  Jinghong Li ,  Christine Qiqing Ouyang ,  Dae-Gyu Park ,  Zhibin Ren ,  Xinhui Wang ,  Haizhou Yin

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.

公开(公告)号：US20080246056A1

公开(公告)日：2008-10-09

申请号：US11697806

申请日：2007-04-09

Applicant: Victor W. C. Chan ,  Thomas W. Dyer ,  Sunfei Fang ,  Jinghong Li ,  Teck J. Tang ,  Henry K. Utomo ,  Jiang Yan

Inventor： Victor W. C. Chan ,  Thomas W. Dyer ,  Sunfei Fang ,  Jinghong Li ,  Teck J. Tang ,  Henry K. Utomo ,  Jiang Yan

IPC: H01L29/778 ,  H01L21/336

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843

Abstract: Methods of forming a suicide in an embedded silicon germanium (eSiGe) source/drain region using a suicide prevention spacer overlapping an interface between the eSiGe and the silicon channel, and a related PFET with an eSiGe source/drain region and a compressive stress liner in close proximity to a silicon channel thereof, are disclosed. In one embodiment, a method includes providing a gate having a nitrogen-containing spacer adjacent thereto and an epitaxially grown silicon germanium (eSiGe) region adjacent to a silicon channel of the gate; removing the nitrogen-containing spacer that does not extend over the interface between the eSiGe source/drain region and the silicon channel; forming a single silicide prevention spacer about the gate, the single silicide prevention spacer overlapping the interface; and forming the silicide in the eSiGe source/drain region using the single silicide prevention spacer to prevent the silicide from forming in at least an extension area of the silicon channel.

Abstract translation: 在嵌入式硅锗（eSiGe）源极/漏极区域中使用与eSiGe和硅沟道之间的界面重叠的防止硅化物的衬垫形成硅化物的方法以及具有eSiGe源极/漏极区域和压应力衬垫的相关PFET 公开了其接近硅通道的方式。 在一个实施例中，一种方法包括提供具有与其相邻的含氮隔离物的栅极和与栅极的硅沟道相邻的外延生长的硅锗（eSiGe）区域; 去除不在eSiGe源极/漏极区域和硅沟道之间的界面上延伸的含氮隔离物; 在栅极周围形成单个硅化物防止间隔物，单个硅化物防止间隔物与界面重叠; 以及使用单个硅化物防止间隔物在eSiGe源极/漏极区域中形成硅化物，以防止硅化物在硅沟道的至少延伸区域中形成。