公开(公告)号：US5526502A

公开(公告)日：1996-06-11

申请号：US39760

申请日：1993-03-30

申请人： Shinichi Yoshida ,  Souichi Miyata ,  Tsuyoshi Muramatsu

发明人： Shinichi Yoshida ,  Souichi Miyata ,  Tsuyoshi Muramatsu

IPC分类号： G06F12/00 ,  G06F15/82 ,  G09G5/36 ,  G09G5/39 ,  G06F12/10 ,  G06F3/023

CPC分类号： G09G5/39 ,  G09G5/36

摘要： A memory interface device capable of memory accessing suitable for video image signal processing and memory accessing designating an arbitrary address. The interface includes an input scrambler for rewriting the generation number of an input data packet utilizing first data and/or second data when the instruction code of the input data packet is a table conversion instruction, and otherwise outputting the input data packet as it is, and a memory accessing circuit accessing an image memory using the generation number of the applied input data packet as an address and outputting the result of accessing. The device produces and outputs an output data packet from the result of accessing output from the memory accessing circuit and the input data packet.

摘要翻译： 一种存储器接口设备，能够进行存储器访问，适用于指定任意地址的视频图像信号处理和存储器访问。 接口包括输入扰码器，用于当输入数据分组的指令代码是表格转换指令时，利用第一数据和/或第二数据重写输入数据分组的生成数，否则直接输出输入数据分组， 以及存储器访问电路，使用所施加的输入数据包的生成号作为地址访问图像存储器，并输出访问结果。 该装置根据从存储器访问电路和输入数据包的输出访问结果产生输出数据包。

公开(公告)号：US5511215A

公开(公告)日：1996-04-23

申请号：US141210

申请日：1993-10-26

申请人： Toshiaki Terasaka ,  Tsuyoshi Muramatsu ,  Souichi Miyata ,  Tatsuyuki Kuwabara ,  Masaharu Tomita ,  Kiyotaka Nagamura ,  Takao Nakamura

发明人： Toshiaki Terasaka ,  Tsuyoshi Muramatsu ,  Souichi Miyata ,  Tatsuyuki Kuwabara ,  Masaharu Tomita ,  Kiyotaka Nagamura ,  Takao Nakamura

IPC分类号： G06F9/44 ,  G06F11/34 ,  G06F11/36 ,  G06F15/82 ,  G06F9/00

CPC分类号： G06F11/3652 ,  G06F11/3476 ,  G06F11/3495 ,  G06F11/3636 ,  G06F15/825 ,  G06F9/4436

摘要： A data processing system includes a data driven processor for carrying out a plurality of different information processing in parallel using respective plurality of provided data packets, a router, and a plurality of von Neumann processors. When a von Neumann processor provides program data packets to the data driven processor via the router to carry out program loading in the data driven processor, another von Neumann processor provides to the data driven processor a data packet storing dumping information via the router. The data driven processor dumps and provides a loaded program data according to the dumping instruction of the provided packet. Therefore, a plurality of von Neumann processors can be connected on-line to at least one data driven processor to carry out in parallel a plurality of different types of data transfer between the data driven processor and each von Neumann processor. These transfers include: (1) dumping a loaded program data packet to a von Neumann processor during loading of other program data packets for on-line verification of proper loading; and (2) outputting an operation result, of an operation process performed by the data driven processor, to the von Neumann processor for verification of proper operation processing during the continued operation processing of the data driven processor.

摘要翻译： 数据处理系统包括数据驱动处理器，用于使用相应的多个提供的数据分组，路由器和多个冯诺依曼处理器并行地执行多个不同的信息处理。 当冯·诺依曼处理器通过路由器向数据驱动处理器提供程序数据分组以在数据驱动处理器中执行程序加载时，另一个冯·诺依曼处理器通过路由器向数据驱动的处理器提供存储转储信息的数据分组。 数据驱动处理器根据提供的数据包的转储指令转储并提供加载的程序数据。 因此，多个冯诺依曼处理器可以在线连接到至少一个数据驱动处理器，以并行地在数据驱动处理器和每个冯诺依曼处理器之间并行执行多种不同类型的数据传输。 这些转移包括：（1）在加载其他程序数据包以便正确加载的在线验证时，将加载的程序数据包转储给冯·诺依曼处理器; 以及（2）将由数据驱动处理器执行的操作处理的操作结果输出到冯诺依曼处理器，以在数据驱动处理器的连续操作处理期间验证正确的操作处理。

公开(公告)号：US5373204A

公开(公告)日：1994-12-13

申请号：US113824

申请日：1993-08-31

申请人： Tsuyoshi Muramatsu ,  Manabu Onozaki

发明人： Tsuyoshi Muramatsu ,  Manabu Onozaki

IPC分类号： G06F13/00 ,  G06F5/08 ,  G06F13/36 ,  G06F15/82 ,  G11C7/22 ,  H03K19/096

CPC分类号： G06F5/08 ,  G11C7/22

摘要： A self-timed clocking transfer control circuit includes a flipflop for storing a transition of a transfer request signal to an L level and outputting an H level signal, an inverter for applying a transfer acknowledge signal to a preceding stage, a 5-input NAND gate, and a second signal output circuit for applying a transfer request signal to a succeeding stage in response to a transition of the output of the 5-input NAND gate to the L level. The 5-input NAND gate does not output the L level unless the transfer request signal from the preceding stage, the output of the flipflop, the transfer acknowledge signal from the succeeding stage, the transfer request signal output by the self-timed clocking transfer control circuit itself, and the prohibition signal are all in the H level. Setting the prohibition signal to the L level, self-synchronous type transfer control can be prohibited. A circuit for generating such a prohibition signal based on a signal for setting an operational mode, a clock signal, and the transfer request signal from the preceding stage may additionally be provided.

摘要翻译： 自定时钟传输控制电路包括用于存储转移请求信号转换为L电平并输出H电平信号的触发器，用于向前级施加传送确认信号的反相器，5输入NAND门 以及第二信号输出电路，用于响应于5输入NAND门的输出到L电平而将转移请求信号施加到后级。 5输入NAND门不输出L电平，除非来自前一级的传送请求信号，触发器的输出，来自后级的传送确认信号，通过自定时钟传输控制输出的传送请求信号 电路本身，禁止信号都处于H电平。 将禁止信号设置为L电平，可以禁止自同步型传输控制。 可以另外提供用于基于用于设置来自前一级的操作模式，时钟信号和传送请求信号的信号来产生这种禁止信号的电路。

公开(公告)号：US5323387A

公开(公告)日：1994-06-21

申请号：US497221

申请日：1990-03-22

申请人： Souichi Miyata ,  Tsuyoshi Muramatsu

发明人： Souichi Miyata ,  Tsuyoshi Muramatsu

IPC分类号： H04L12/56

CPC分类号： H04L45/00 ,  H04L45/16

摘要： A data transmission apparatus includes one input-side transmission path and a plurality of output-side transmission paths. The input-side transmission path includes a plurality of handshaking-type data transmission paths provided in series. Each of the output-side transmission paths includes a plurality of handshaking-type data transmission paths provided in series. Data to be transmitted includes an identifier for designation any or all of the plurality of output-side transmission paths. A comparison and determination logic portion determines whether the identifier included in the data designates any of the plurality of output-side transmission paths or all of them. A control portion sends the data supplied from the input-side transmission path to any or all of the plurality of output-side transmission paths, in response to a signal outputted from the comparison and determination logic portion.

摘要翻译： 数据传输装置包括一个输入侧传输路径和多个输出侧传输路径。 输入侧传输路径包括串联提供的多个握手型数据传输路径。 每个输出侧传输路径包括串联提供的多个握手型数据传输路径。 要发送的数据包括用于指定多个输出侧传输路径中的任何一个或全部的标识符。 比较和确定逻辑部分确定包括在数据中的标识符是否指定多个输出侧传输路径中的任何一个或全部。 控制部分响应于从比较和确定逻辑部分输出的信号，将从输入侧传输路径提供的数据发送到多个输出侧传输路径中的任何一个或全部。

公开(公告)号：US07340586B2

公开(公告)日：2008-03-04

申请号：US10977401

申请日：2004-11-01

申请人： Yasufumi Itoh ,  Tsuyoshi Muramatsu

发明人： Yasufumi Itoh ,  Tsuyoshi Muramatsu

IPC分类号： G06F11/30

CPC分类号： G06F9/4494

摘要： A data-driven type information processor includes a ifinction processor manipulating contents in a data packet, a program storage unit storing a data flow program used by the function processor, and a branch unit controlling data flow whether to allow flow of a data packet within the processor or to provide the data packet to the outside thereof When a program is debugged, the portion of the program where a data packet is to be dumped (and checked) is directly designated by writing an instruction in a program that is stored in advance in the program storage unit. When the instruction code is encountered, the packet is dumped to the outside so that debugging of the program can be carried out by confirming the contents in the data packet that is output.

摘要翻译： 数据驱动型信息处理器包括处理数据分组中的内容的函数处理器，存储由功能处理器使用的数据流程序的程序存储单元以及控制数据流的分支单元是否允许数据分组内的数据分组的流动 处理器或向其外部提供数据分组当调试程序时，通过在预先存储的程序中写入指令来直接指定要转储（并检查）数据分组的程序部分 程序存储单元。 当遇到指令代码时，将数据包转储到外部，以便通过确认输出的数据包中的内容来执行程序的调试。

公开(公告)号：US20050102490A1

公开(公告)日：2005-05-12

申请号：US10977401

申请日：2004-11-01

申请人： Yasufumi Itoh ,  Tsuyoshi Muramatsu

发明人： Yasufumi Itoh ,  Tsuyoshi Muramatsu

IPC分类号： G06F11/28 ,  G06F9/44 ,  G06F15/00 ,  G06F15/82 ,  H04L12/701

CPC分类号： G06F9/4494

摘要： A data-driven type information processor includes a function processor manipulating contents in a data packet, a program storage unit storing a data flow program used by the function processor, and a branch unit controlling data flow whether to allow flow of a data packet within the processor or to provide the data packet to the outside thereof. An instruction code to provide the data packet storing a result of an operation being performed in the data-driven type information processor being executing the data flow program through the branch unit to the outside of the processor while holding the result of operation is prepared. Then, the instruction code is described in a desired portion in the data flow program. The function processor also attains an operation function to execute the instruction code.

摘要翻译： 数据驱动型信息处理器包括操作数据包中的内容的功能处理器，存储由功能处理器使用的数据流程序的程序存储单元，以及控制数据流的分支单元是否允许数据包内的数据包流 处理器或将数据包提供给其外部。 准备存储在数据驱动类型信息处理器中执行的操作结果的数据分组的指令代码，其中通过分支单元在保持操作结果的同时执行数据流程序到处理器的外部。 然后，在数据流程序的期望部分中描述指令代码。 功能处理器还具有执行指令代码的操作功能。

公开(公告)号：US5956517A

公开(公告)日：1999-09-21

申请号：US618376

申请日：1996-03-19

申请人： Toshiya Okamoto ,  Tsuyoshi Muramatsu

发明人： Toshiya Okamoto ,  Tsuyoshi Muramatsu

IPC分类号： G06F15/82 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/4436

摘要： A data driven information processor includes an operation processor unit for prestoring a data flow program and carrying out processing, and a storage microprocessor unit having a plurality of data memories including external data memories for inputting/outputting data to and from the operation processor unit. In the storage microprocessor unit, a plurality of data memories are accessed, in parallel, based on the content of an applied data packet for a single access time. The result of each access is operated in accordance with the content of the data packet. Finally, the subsequent program is read from a data flow program prestored in the storage microprocessor unit so that access to the plurality of data memories and processing of a result of the access continue in the storage microprocessor unit. Thus, in the information processor, parallel access to a plurality of data memories can be achieved by program control independent of program control by the operation processor unit.

摘要翻译： 数据驱动信息处理器包括用于预先存储数据流程序和执行处理的操作处理器单元，以及具有多个数据存储器的存储微处理器单元，该数据存储器包括用于向/从操作处理器单元输入/输出数据的外部数据存储器。 在存储微处理器单元中，基于用于单个访问时间的应用数据分组的内容并行地访问多个数据存储器。 每个访问的结果根据数据包的内容进行操作。 最后，从预先存储在存储微处理器单元中的数据流程序读取随后的程序，从而在存储微处理器单元中继续访问多个数据存储器以及访问结果的处理。 因此，在信息处理器中，可以通过独立于操作处理器单元的程序控制的程序控制来实现对多个数据存储器的并行访问。

公开(公告)号：US5872991A

公开(公告)日：1999-02-16

申请号：US720965

申请日：1996-10-10

申请人： Toshiya Okamoto ,  Tsuyoshi Muramatsu

发明人： Toshiya Okamoto ,  Tsuyoshi Muramatsu

IPC分类号： G06F9/38 ,  G06F9/44 ,  G06F12/00 ,  G06F15/82

CPC分类号： G06F9/4436

摘要： A data driven information processor includes an input control portion for producing a first data packet including common identification information and a plurality of pieces of data, a junction portion for controlling input of the first data packet and a second data packet, a firing control portion for detecting data to be paired with data in the selected data packet and outputting paired data, an operation processing portion for operating the paired data, a program storage portion for producing and outputting a second data packet based on a result of operation, and a branching portion for controlling whether to output the second data packet to the junction portion or to another data driven information processor. A plurality of such data driven information processors are connected for parallel processing.

摘要翻译： 数据驱动信息处理器包括用于产生包括公共识别信息和多条数据的第一数据包的输入控制部分，用于控制第一数据包的输入和第二数据包的接合部分，用于 检测与所选数据分组中的数据配对并输出成对数据的数据，用于操作配对数据的操作处理部分，用于基于操作结果产生和输出第二数据分组的程序存储部分，以及分支部分 用于控制是否将第二数据包输出到接合部分或另一数据驱动信息处理器。 多个这样的数据驱动信息处理器被连接用于并行处理。

公开(公告)号：US5860130A

公开(公告)日：1999-01-12

申请号：US636579

申请日：1996-04-23

申请人： Hidekazu Yamanaka ,  Tsuyoshi Muramatsu

发明人： Hidekazu Yamanaka ,  Tsuyoshi Muramatsu

IPC分类号： G06F13/12 ,  G06F9/345 ,  G06F12/00 ,  G06F15/82 ,  G06F9/28

CPC分类号： G06F9/345

摘要： A memory interface apparatus includes a plurality of data memories MEMs, and address modification units AMDs and memory access units I/Fs respectively corresponding to the plurality of data memories MEMs. Each address modification unit AMD has an offset table OFT for pre-storing a plurality of offsets, reads an offset from the table OFT based on received second data D2, modifies an address indicated by a received generation number GN using the read offset, and applies a resultant address to a corresponding memory access unit I/F. Each memory access unit I/F accesses a memory MEM based on the applied address, according to a received operation code C. Each result of access is applied in parallel to an operation unit ALU, which in turn performs operation of the applied result according to an operation code C. Thus, operation processing which compounds access to a memory can be carried out, utilizing parallelism in processing sufficiently.

摘要翻译： 存储器接口装置包括分别对应于多个数据存储器MEM的多个数据存储器MEM和地址修改单元AMD和存储器存取单元I / F。 每个地址修改单元AMD具有用于预存储多个偏移量的偏移表OFT，基于接收到的第二数据D2从表OFT读取偏移量，使用读取的偏移修改由接收到的代数GN指示的地址，并应用 结果地址到对应的存储器存取单元I / F。 每个存储器存取单元I / F根据所接收的操作代码C，根据所应用的地址访问存储器MEM.访问结果与操作单元ALU并行地应用，操作单元ALU依次执行应用结果的操作 操作代码C.因此，可以执行化合物访问存储器的操作处理，利用处理中的并行性充分。

公开(公告)号：US5761737A

公开(公告)日：1998-06-02

申请号：US412303

申请日：1995-03-29

申请人： Ryuji Kadosumi ,  Tsuyoshi Muramatsu

发明人： Ryuji Kadosumi ,  Tsuyoshi Muramatsu

IPC分类号： G06F15/82 ,  G06F9/44 ,  G06F13/12

CPC分类号： G06F9/4436

摘要： A data driven type information processing apparatus includes a generation number translation table and a generation number translation circuit. The generation number translation table includes translated generation numbers. The translated generation numbers have been calculated in advance in relation to the generation numbers by a prescribed functional relation. An address of the translated generation number is specified by a prescribed calculation on the generation number. In response to a generation number translation instruction, the generation number translation circuit accesses the generation number translation table based on the content of the generation number field of the applied data packet, and reads the corresponding translated generation number. Further, the generation number translation circuit rewrites the generation number of the applied data packet with the read translated generation number. The generation number can be translated easily with fewer number of instructions, in accordance with a prescribed functional relation. The translated generation number can be prepared in advance with a desired precision. As a result, a data driven type information processing apparatus by which generation number can be translated easily at high speed with high precision can be obtained.

摘要翻译： 数据驱动型信息处理装置包括代数转换表和代数转换电路。 代号转换表包括翻译的代数。 已经按照规定的函数关系，预先计算了与代数相关的翻译代数。 通过对生成号码的规定计算来指定翻译后的编号的地址。 响应于代号转换指令，生成号码转换电路基于所应用的数据包的生成号字段的内容来访问生成号码转换表，并读取相应的翻译的生成号码。 此外，生成号码转换电路以读出的翻译代数重写应用数据包的生成号码。 根据规定的功能关系，可以轻松地转换代号数量较少的指令。 可以预期地以所需的精度准备翻译的代数。 结果，可以获得能够高精度地容易地生成代数的数据驱动型信息处理装置。