公开(公告)号：US20090053865A1

公开(公告)日：2009-02-26

申请号：US11841269

申请日：2007-08-20

申请人： Frank Scott Johnson ,  Shaofeng Yu

发明人： Frank Scott Johnson ,  Shaofeng Yu

IPC分类号： H01L21/8238

CPC分类号： H01L29/7847 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6659 ,  H01L29/7833

摘要： Source and drain regions are formed in a first-type semiconductor device. Then, a high tensile stress capping layer is formed over the source and drain regions. A thermal process is then performed to re-crystallize the source and drain regions and to introduce tensile strain into the source and drain regions of the first-type semiconductor device. Afterwards, source and drain regions are formed in a second-type semiconductor device. Then, a high compressive stress capping layer is formed over the source and drain regions of the second-type semiconductor device. A thermal process is performed to re-crystallize the source and drain regions and to introduce compressive strain into the source and drain regions of the second-type semiconductor device.

摘要翻译： 源区和漏区形成在第一类半导体器件中。 然后，在源极和漏极区域上形成高拉伸应力覆盖层。 然后进行热处理以使源极和漏极区域再结晶，并将拉伸应变引入第一类型半导体器件的源极和漏极区域。 之后，源区和漏区形成在第二类半导体器件中。 然后，在第二类型半导体器件的源极和漏极区域上形成高压缩应力覆盖层。 执行热处理以使源区和漏区重新结晶，并将压缩应变引入第二类半导体器件的源区和漏区。

公开(公告)号：US20090032877A1

公开(公告)日：2009-02-05

申请号：US11832037

申请日：2007-08-01

申请人： Mark R. Visokay ,  Shaofeng Yu

发明人： Mark R. Visokay ,  Shaofeng Yu

IPC分类号： H01L21/8236 ,  H01L29/78

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L29/7847

摘要： A method of manufacturing a semiconductor device includes forming transistors including gate electrodes and source/drain regions over a substrate. A protective layer is placed over the source/drain regions and the gate electrodes. A portion of the protective layer is removed to expose a portion of the gate electrodes. The exposed portions of the gate electrodes are amorphized, and remaining portions of the protective layer located over the source/drain regions are removed. A stress memorization layer is formed over the gate electrodes, and the substrate is annealed in the presence of the stress memorization layer to at least reduce an amorphous content of the gate electrodes. The stress memorization layer is removed subsequent to the annealing.

摘要翻译： 制造半导体器件的方法包括在衬底上形成包括栅电极和源/漏区的晶体管。 保护层放置在源极/漏极区域和栅极电极之上。 去除保护层的一部分以露出栅电极的一部分。 栅电极的露出部分是非晶化的，并且去除位于源极/漏极区上方的保护层的剩余部分。 在栅电极上形成应力记忆层，并且在应力存储层的存在下对基板进行退火，以至少降低栅电极的无定形含量。 在退火之后去除应力记忆层。

公开(公告)号：US20090020791A1

公开(公告)日：2009-01-22

申请号：US11778321

申请日：2007-07-16

申请人： Shaofeng Yu ,  Juanita DeLoach ,  Brian A. Smith ,  Yaw S. Obeng ,  Scott Gregory Bushman

发明人： Shaofeng Yu ,  Juanita DeLoach ,  Brian A. Smith ,  Yaw S. Obeng ,  Scott Gregory Bushman

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： Exemplary embodiments provide IC CMOS devices having dual stress layers and methods for their manufacture using a buffer layer stack between the two types of the stress layers. The buffer layer stack can include multiple buffer layers formed between a first type stress layer (e.g., a tensile stress layer) and a second type stress layer (e.g., a compressive stress layer) during the CMOS fabrication. Specifically, the buffer layer stack can be formed after the etching process of the first type stress layer but prior to the etching process of the second type stress layer, and thus to protect the etched first type stress layer during the subsequent etching process of the overlaid second type stress layer. In addition, a portion of the buffer layer stack can be formed between, for example, the compressive stress layer and the underlying PMOS device to enhance their adhesion.

摘要翻译： 示例性实施例提供了具有双应力层的IC CMOS器件及其制造方法，使用两种类型的应力层之间的缓冲层堆叠。 缓冲层堆叠可以包括在CMOS制造期间在第一类型应力层（例如，拉伸应力层）和第二类型应力层（例如，压应力层）之间形成的多个缓冲层。 具体地说，缓冲层堆叠可以在第一类应力层的蚀刻工艺之后但是在第二种应力层的蚀刻工艺之前形成，从而在重叠的随后的蚀刻工艺期间保护蚀刻的第一类型应力层 第二类应力层。 此外，缓冲层堆叠的一部分可以形成在例如压应力层和下面的PMOS器件之间，以增强其粘附性。

公开(公告)号：US07253049B2

公开(公告)日：2007-08-07

申请号：US11017469

申请日：2004-12-20

申请人： Jiong-Ping Lu ,  Shaofeng Yu ,  Haowen Bu ,  Lindsey H. Hall ,  Mark R. Visokay

发明人： Jiong-Ping Lu ,  Shaofeng Yu ,  Haowen Bu ,  Lindsey H. Hall ,  Mark R. Visokay

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method may include implanting dopants into a gate polysilicon layer 115 before forming the protection layer 215.

摘要翻译： 一种用于在半导体衬底20上制造PMOS和NMOS晶体管60,70的方法，其包括在源/漏硅化物120形成期间在栅电极层110上方具有栅极保护层210。 该方法可以包括在形成保护层215之前将掺杂剂注入到栅极多晶硅层115中。

公开(公告)号：US20070161246A1

公开(公告)日：2007-07-12

申请号：US11382639

申请日：2006-05-10

申请人： Yaw Obeng ,  Jiong-Ping Lu ,  Shaofeng Yu

发明人： Yaw Obeng ,  Jiong-Ping Lu ,  Shaofeng Yu

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31111

摘要： A method for removing dielectric material 50 from a semiconductor wafer 20 that contains metal silicide 60 or 90. The method includes performing a selective etch 202 of the semiconductor wafer 20 using an organic semi-aqueous solvent-based etchant until the dielectric material 50 is substantially removed and then rinsing 204 the semiconductor wafer 20 including a surface, 63 or 93, of the metal silicide, 60 or 90 respectively, of the semiconductor wafer 20.

摘要翻译： 从包含金属硅化物60或90的半导体晶片20去除介电材料50的方法。 该方法包括使用有机半水溶剂型蚀刻剂来执行半导体晶片20的选择性蚀刻202，直到电介质材料50被基本除去，然后冲洗204包括金属的表面63或93的半导体晶片20 硅化物，60或90分别为半导体晶片20。

公开(公告)号：US07189627B2

公开(公告)日：2007-03-13

申请号：US10921532

申请日：2004-08-19

申请人： Zhiqiang Wu ,  Shaofeng Yu ,  C. Rinn Cleavelin

发明人： Zhiqiang Wu ,  Shaofeng Yu ,  C. Rinn Cleavelin

IPC分类号： H01L21/76

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/11

摘要： A technique is disclosed for increasing the width of a transistor (300) while the transistor itself may be scaled down. The transistor width (382) is increased by forming recesses (352) within shallow trench isolation (STI) regions (328) adjacent to the transistor (300). The recesses (352) provide an area that wraps around the transistor and thereby increases the width (382) of the transistor (300). This wraparound area provides additional space for dopant atom deposition, which facilitates a reduction in random dopant fluctuation (RDF). In this manner, transistors formed in accordance with one or more aspects of the present invention, may yield improved performance when incorporated into SRAM since the probability that such transistors will be more closely matched is increased.

摘要翻译： 公开了一种用于增加晶体管（300）的宽度的技术，同时可以缩小晶体管本身。 通过在与晶体管（300）相邻的浅沟槽隔离（STI）区域（328）内形成凹槽（352）来增加晶体管宽度（382）。 凹部（352）提供围绕晶体管的区域，从而增加晶体管（300）的宽度（382）。 该环绕区域为掺杂剂原子沉积提供了额外的空间，这有助于随机掺杂剂波动（RDF）的减少。 以这种方式，根据本发明的一个或多个方面形成的晶体管可以在并入SRAM时产生改善的性能，因为这种晶体管将更加紧密匹配的可能性增加。

公开(公告)号：US07157358B2

公开(公告)日：2007-01-02

申请号：US10884665

申请日：2004-07-02

申请人： Lindsey Hall ,  Haowen Bu ,  Shaofeng Yu

发明人： Lindsey Hall ,  Haowen Bu ,  Shaofeng Yu

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, forming a polysilicon gate electrode (250) over a substrate (210) and forming a protective layer (260) over the polysilicon gate electrode (250) to provide a capped polysilicon gate electrode (230). The method further includes forming a protective oxide (510) on a surface proximate the polysilicon gate electrode (250), and removing the protective oxide (510) using a wet etch, the wet etch not having a substantial impact on the protective layer (260).

摘要翻译： 本发明提供一种制造半导体器件的方法及其制造方法，该集成电路包括该半导体器件。 制造半导体器件的方法以及其它可能的步骤，在衬底（210）上形成多晶硅栅电极（250）并在多晶硅栅电极（250）上形成保护层（260），以提供封盖的多晶硅栅电极 （230）。 该方法还包括在邻近多晶硅栅极（250）的表面上形成保护氧化物（510），并且使用湿蚀刻去除保护氧化物（510），湿法蚀刻不会对保护层（260 ）。

公开(公告)号：US20060040462A1

公开(公告)日：2006-02-23

申请号：US10921532

申请日：2004-08-19

申请人： Zhiqiang Wu ,  Shaofeng Yu ,  C. Cleavelin

发明人： Zhiqiang Wu ,  Shaofeng Yu ,  C. Cleavelin

IPC分类号： H01L21/76

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/11

摘要： A technique is disclosed for increasing the width of a transistor (300) while the transistor itself may be scaled down. The transistor width (382) is increased by forming recesses (352) within shallow trench isolation (STI) regions (328) adjacent to the transistor (300). The recesses (352) provide an area that wraps around the transistor and thereby increases the width (382) of the transistor (300). This wraparound area provides additional space for dopant atom deposition, which facilitates a reduction in random dopant fluctuation (RDF). In this manner, transistors formed in accordance with one or more aspects of the present invention, may yield improved performance when incorporated into SRAM since the probability that such transistors will be more closely matched is increased.

摘要翻译： 公开了一种用于增加晶体管（300）的宽度的技术，同时可以缩小晶体管本身。 通过在与晶体管（300）相邻的浅沟槽隔离（STI）区域（328）内形成凹槽（352）来增加晶体管宽度（382）。 凹部（352）提供围绕晶体管的区域，从而增加晶体管（300）的宽度（382）。 该环绕区域为掺杂剂原子沉积提供了额外的空间，这有助于随机掺杂剂波动（RDF）的减少。 以这种方式，根据本发明的一个或多个方面形成的晶体管可以在并入SRAM时产生改善的性能，因为这种晶体管将更加紧密匹配的可能性增加。

公开(公告)号：US20050215038A1

公开(公告)日：2005-09-29

申请号：US10884665

申请日：2004-07-02

申请人： Lindsey Hall ,  Haowen Bu ,  Shaofeng Yu

发明人： Lindsey Hall ,  Haowen Bu ,  Shaofeng Yu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/44 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, forming a polysilicon gate electrode (250) over a substrate (210) and forming a protective layer (260) over the polysilicon gate electrode (250) to provide a capped polysilicon gate electrode (230). The method further includes forming a protective oxide (510) on a surface proximate the polysilicon gate electrode (250), and removing the protective oxide (510) using a wet etch, the wet etch not having a substantial impact on the protective layer (260).

摘要翻译： 本发明提供一种制造半导体器件的方法及其制造方法，该集成电路包括该半导体器件。 制造半导体器件的方法以及其它可能的步骤，在衬底（210）上形成多晶硅栅电极（250）并在多晶硅栅电极（250）上形成保护层（260），以提供封盖的多晶硅栅电极 （230）。 该方法还包括在邻近多晶硅栅极（250）的表面上形成保护氧化物（510），并且使用湿蚀刻去除保护氧化物（510），湿法蚀刻不会对保护层（260 ）。

公开(公告)号：US20050202312A1

公开(公告)日：2005-09-15

申请号：US11122685

申请日：2005-05-04

申请人： Miriam Reshotko ,  Shaofeng Yu ,  Bruce Block

发明人： Miriam Reshotko ,  Shaofeng Yu ,  Bruce Block

IPC分类号： H01L27/14 ,  H01L29/72 ,  H01L31/0224 ,  H01M4/36 ,  H01M4/48

CPC分类号： H01L31/03529 ,  H01L31/0224 ,  H01L31/1085 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A photosensitive device for enabling high speed detection of electromagnetic radiation. The device includes recessed electrodes for providing a generally homogeneous electric field in an active region. Carriers generated in the active region are detected using the recessed electrodes.