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    TARGET ISSUE INTERVALS
    41.
    发明申请
    TARGET ISSUE INTERVALS 有权
    目标问题间隔

    公开(公告)号：US20130107891A1

    公开(公告)日：2013-05-02

    申请号：US13286391

    申请日：2011-11-01

    申请人： Michael L. Ziegler

    发明人： Michael L. Ziegler

    IPC分类号： H04L12/54

    CPC分类号： H04L12/4633

    摘要： Techniques for using target issue intervals are provided. Request messages may identify the size of a data packet. A target issue interval may be determined based on the request messages. The target issue interval may be used to insert a delay between sending subsequent request messages.

    摘要翻译： 提供了使用目标问题间隔的技术。 请求消息可以标识数据分组的大小。 可以基于请求消息来确定目标问题间隔。 目标问题间隔可用于在发送后续请求消息之间插入延迟。

    RESPONSE MESSAGES BASED ON PENDING REQUESTS
    42.
    发明申请
    RESPONSE MESSAGES BASED ON PENDING REQUESTS 审中-公开
    基于待定请求的响应消息

    公开(公告)号：US20130028266A1

    公开(公告)日：2013-01-31

    申请号：US13194037

    申请日：2011-07-29

    申请人： Michael L. Ziegler ,  Steven Glen Jorgensen ,  Jonathan M. Watts

    发明人： Michael L. Ziegler ,  Steven Glen Jorgensen ,  Jonathan M. Watts

    IPC分类号： H04L12/56

    CPC分类号： H04L49/10 ,  H04L49/9063

    摘要： Techniques are provided for sending response messages based on pending requests. A request message identifying a data packet may be received. A pending request structure may be used to determine output queues that are in need of the data packet identified in the request message. A response message may be sent indicating if the request message is being refused based on the output queues.

    摘要翻译： 提供了基于待决请求发送响应消息的技术。 可以接收标识数据分组的请求消息。 可以使用待决请求结构来确定需要在请求消息中标识的数据包的输出队列。 可以发送响应消息，指示是否基于输出队列拒绝请求消息。

    Processing element having dual control stores to minimize branch latency
    43.
    发明授权
    Processing element having dual control stores to minimize branch latency 有权
    具有双重控制存储器的处理元件以最小化分支延迟

    公开(公告)号：US08046569B2

    公开(公告)日：2011-10-25

    申请号：US11796810

    申请日：2007-04-30

    申请人： Michael L. Ziegler

    发明人： Michael L. Ziegler

    IPC分类号： G06F9/00

    CPC分类号： G06F9/267 ,  G06F9/322

    摘要： Embodiments involve an embedded processing element that fetches at least two possible next instructions (control words) in parallel in one cycle, and executes one of them during the following cycle based on the result of a conditional branch test. Embodiments reduce or avoid branch penalties (zero penalty branches).

    摘要翻译： 实施例涉及在一个周期中并行获取至少两个可能的下一个指令（控制字）的嵌入式处理元件，并且基于条件分支测试的结果在随后的周期中执行它们之一。 实施例减少或避免分支惩罚（零惩罚分支）。

    Method for allowing distributed high performance coherent memory with full error containment
    44.
    发明授权
    Method for allowing distributed high performance coherent memory with full error containment 失效
    允许分布式高性能相干存储器具有全错误容错的方法

    公开(公告)号：US07478262B2

    公开(公告)日：2009-01-13

    申请号：US10664763

    申请日：2003-09-17

    申请人： Kent A. Dickey ,  Michael L. Ziegler

    发明人： Kent A. Dickey ,  Michael L. Ziegler

    IPC分类号： G06F11/00

    CPC分类号： G06F11/0796 ,  G06F11/004 ,  G06F11/0724 ,  G06F11/0772

    摘要： The present invention provides for a method and system for ensuring error containment in packet based systems which are capable of large scaleability. In operation, an error bit travels with each data packet and if the bit is set any device which receives the data packet acts to contain that packet. Thus, the error message travels only as far as the error data and does not stop processing at locations not affected by the error. Any system resource, upon receipt of a set error bit, must act to correct the fault.

    摘要翻译： 本发明提供一种确保能够具有大的可扩展性的基于分组的系统中的错误容纳的方法和系统。 在操作中，错误位与每个数据分组一起传播，并且如果该位被置位，则接收数据分组的任何设备用于包含该分组。 因此，错误消息仅传送到错误数据的一个位置，并且不会在不受错误影响的位置停止处理。 任何系统资源在收到设置的错误位后都必须采取行动来纠正故障。

    Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus
    47.
    发明授权
    Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus 失效
    通过按照在总线上发出的事务的顺序检查一致性来维持高速缓存一致性的多处理器系统

    公开(公告)号：US5530933A

    公开(公告)日：1996-06-25

    申请号：US201463

    申请日：1994-02-24

    申请人： Craig R. Frink ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert D. Odineal ,  James B. Williams ,  Michael L. Ziegler

    发明人： Craig R. Frink ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert D. Odineal ,  James B. Williams ,  Michael L. Ziegler

    IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/06

    CPC分类号： G06F12/0831

    摘要： A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitting coherent transactions on the bus to other processor modules and to the main memory controller. Each processor module detects coherent transactions issued on the bus and performs cache coherency checks for each of the coherent transactions. Each processor module has a coherency queue for storing all transactions issued on the bus and for performing coherency checks for the transactions in first-in, first-out order. When a module transmits a coherent transaction on a bus, it places its own transaction into its own coherency queue.

    摘要翻译： 与具有总线的系统一起使用的一致性方案，主存储器，用于响应于在总线上接收到的事务来访问主存储器的主存储器控制器，以及耦合到总线的一组处理器模块。 每个处理器模块具有高速缓冲存储器，并且能够将总线上的相干事务发送到其他处理器模块和主存储器控制器。 每个处理器模块检测总线上发出的相干事务，并执行每个相干事务的高速缓存一致性检查。 每个处理器模块具有用于存储在总线上发布的所有事务的一致性队列，并且用于以先入先出顺序执行事务的一致性检查。 当模块在总线上传输一致的事务时，它将自己的事务置于自己的一致性队列中。

    Multiple arbitration scheme
    48.
    发明授权
    Multiple arbitration scheme 失效
    多重仲裁方案

    公开(公告)号：US5528766A

    公开(公告)日：1996-06-18

    申请号：US217500

    申请日：1994-03-24

    申请人： Michael L. Ziegler ,  John F. Shelton ,  William R. Bryg

    发明人： Michael L. Ziegler ,  John F. Shelton ,  William R. Bryg

    IPC分类号： G06F13/362 ,  G06F13/36 ,  G06F13/14

    CPC分类号： G06F13/36

    摘要： A multiple round-robin arbitration scheme for a shared bus system that ensures forward progress by each component utilizing the shared bus. In the shared bus system, component modules arbitrate for control of the bus for one or more cycles, and send transactions on the bus during cycles in which they control the bus. The transactions are divided into a set of transaction classes. Certain classes of transactions cannot be issued during certain bus cycles. In certain other cycles, transactions of any class may be issued. The multiple round-robin arbitration scheme ensures forward progress by ensuring that each module seeking to issue a transaction of a given class obtains control of the bus during a cycle when transactions of that class can be issued.

    摘要翻译： 一种共享总线系统的多循环仲裁方案，确保每个组件利用共享总线的前进进程。 在共享总线系统中，组件模块仲裁一个或多个周期的总线控制，并在总线控制总线的周期期间在总线上发送事务。 交易分为一组交易类。 在某些公交车周期内不能发出某些类别的交易。 在某些其他周期中，任何类别的交易都可能被发行。 多轮循环仲裁方案通过确保寻求发出给定类别的交易的每个模块在可以发出该类交易的一个周期内获得对总线的控制，从而确保前进进展。

    Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
    49.
    发明授权
    Digital computer with cache capable of concurrently handling multiple accesses from parallel processors 失效
    具有能够并行处理来自并行处理器的多个访问的缓存的数字计算机

    公开(公告)号：US4794521A

    公开(公告)日：1988-12-27

    申请号：US757859

    申请日：1985-07-22

    申请人： Michael L. Ziegler ,  Jonathan S. Blau ,  Robert L. Fredieu

    发明人： Michael L. Ziegler ,  Jonathan S. Blau ,  Robert L. Fredieu

    IPC分类号： G06F12/08 ,  G06F13/00

    CPC分类号： G06F12/084 ,  G06F12/0859

    摘要： A cache memory capable of concurrently accepting and working on completion of more than one cache access from a plurality of processors connected in parallel. Current accesses to the cache are handled by current-access-completion circuitry which determines whether the current access is capable of immediate completion and either completes the access immediately if so capable or transfers the access to pending-access-completion circuitry if not so capable. The latter circuitry works on completion of pending accesses; it determines and stores for each pending access status information prescribing the steps required to complete the access and redetermines that status information as conditions change. In working on completion of current and pending accesses, the addresses of the accesses are compared to those of memory accesses in progress on the system.

    摘要翻译： 一种高速缓冲存储器，其能够并行地接受并且从并行连接的多个处理器完成多于一个的高速缓存访​​问。 当前访问完成电路由当前访问完成电路来处理对高速缓存的当前访问，该电路确定当前访问是否能够立即完成，并且如果能够执行，则立即完成访问，或者如果不能够将该访问传送到等待访问完成电路。 后者的电路工作在完成未决访问; 它确定并存储规定完成访问所需步骤的每个未决访问状态信息，并根据条件改变重新确定该状态信息。 在完成当前和未完成的访问时，将访问地址与正在进行的存储器访问的地址进行比较。

    Digital computer with multisection cache
    50.
    发明授权
    Digital computer with multisection cache 失效
    带多段缓存的数字电脑

    公开(公告)号：US4783736A

    公开(公告)日：1988-11-08

    申请号：US757853

    申请日：1985-07-22

    申请人： Michael L. Ziegler ,  Robert L. Fredieu

    发明人： Michael L. Ziegler ,  Robert L. Fredieu

    IPC分类号： G06F15/16 ,  G06F9/42 ,  G06F9/44 ,  G06F12/08 ,  G06F15/177 ,  G06F9/00

    CPC分类号： G06F9/4426 ,  G06F12/0851 ,  G06F8/45

    摘要： A digital computer including a plurality of memory elements, the memory elements being interleaved (i.e., each is assigned memory addresses on the basis of a low order portion of the memory address), a plurality of processors connected in parallel, the processors each having means for initiating an access of data from any of the memory elements simultaneously with accesses of other processors, the memory elements each being capable of accepting an access from just one of the processors during a given cycle, and the memory elements being interleaved so that the memory access patterns generated at a stride of one and a stride of two each meet the conditions that (1) the pattern will tolerate being offset with respect to an identical pattern by a desired offset and any multiple of the offset (wherein tolerating means that no memory access conflicts arise, i.e., more than one processor simultaneously attempting to access the same memory element) and (2) the pattern includes sufficient conflicts at offsets other than the desired offset to force the processors to assume a relationship wherein the desired offset is achieved, so that the processor is able to access a different memory element simultaneously without creating access conflicts.

    摘要翻译： 一种包括多个存储元件的数字计算机，存储器元件被交错（即，基于存储器地址的低阶部分分配存储器地址），并行连接的多个处理器，每个处理器具有装置 用于启动来自任何存储器元件的数据与其他处理器的访问同时访问，每个存储器元件能够在给定周期期间仅接收来自处理器中的一个的访问，并且存储器元件被交织，使得存储器 在步幅1和步幅2中产生的访问模式都满足以下条件：（1）模式将容忍相对于相同模式偏移期望的偏移量和偏移的任何倍数（其中容忍意味着没有记忆 出现访问冲突，即，多个处理器同时尝试访问相同的存储器元件）和（2）该模式包括足够的conf 以除了期望的偏移之外的偏移量强制处理器呈现其中实现期望的偏移的关系，使得处理器能够同时访问不同的存储元件而不产生访问冲突。