公开(公告)号：US5528766A

公开(公告)日：1996-06-18

申请号：US217500

申请日：1994-03-24

申请人： Michael L. Ziegler ,  John F. Shelton ,  William R. Bryg

发明人： Michael L. Ziegler ,  John F. Shelton ,  William R. Bryg

IPC分类号： G06F13/362 ,  G06F13/36 ,  G06F13/14

CPC分类号： G06F13/36

摘要： A multiple round-robin arbitration scheme for a shared bus system that ensures forward progress by each component utilizing the shared bus. In the shared bus system, component modules arbitrate for control of the bus for one or more cycles, and send transactions on the bus during cycles in which they control the bus. The transactions are divided into a set of transaction classes. Certain classes of transactions cannot be issued during certain bus cycles. In certain other cycles, transactions of any class may be issued. The multiple round-robin arbitration scheme ensures forward progress by ensuring that each module seeking to issue a transaction of a given class obtains control of the bus during a cycle when transactions of that class can be issued.

摘要翻译： 一种共享总线系统的多循环仲裁方案，确保每个组件利用共享总线的前进进程。 在共享总线系统中，组件模块仲裁一个或多个周期的总线控制，并在总线控制总线的周期期间在总线上发送事务。 交易分为一组交易类。 在某些公交车周期内不能发出某些类别的交易。 在某些其他周期中，任何类别的交易都可能被发行。 多轮循环仲裁方案通过确保寻求发出给定类别的交易的每个模块在可以发出该类交易的一个周期内获得对总线的控制，从而确保前进进展。

公开(公告)号：US06049851A

公开(公告)日：2000-04-11

申请号：US196618

申请日：1994-02-14

申请人： William R. Bryg ,  Kenneth K. Chan ,  Eric Delano ,  John F. Shelton

发明人： William R. Bryg ,  Kenneth K. Chan ,  Eric Delano ,  John F. Shelton

IPC分类号： G06F12/08 ,  G06F9/34

CPC分类号： G06F12/0831

摘要： A double cache snoop mechanism in uniprocessor computer systems having a cache and coherent I/O and multiprocessor computer systems reduces the number of cycles that a processor is stalled during a coherency check. The snoop mechanism splits each coherency check, such that a read-only check is first sent to the cache subsystem., and a read-write check is sent thereafter only if there is a cache hit during the read-only check, and there is the need to modify the cache. Average processor pipeline stall time is reduced even though a cache hit results in an additional coherency check because most coherency checks do not result in a cache hit.

摘要翻译： 具有高速缓存和相干I / O和多处理器计算机系统的单处理器计算机系统中的双缓存窥探机制减少了在一致性检查期间处理器停顿的周期数。 侦听机制分割每个相关性检查，以便首先将只读检查发送到高速缓存子系统，然后只有在只读检查期间存在高速缓存命中时才会发送读写检查，并且存在 需要修改缓存。 即使缓存命中导致额外的一致性检查，平均处理器流水线停止时间也减少，因为大多数一致性检查不会导致缓存命中。

公开(公告)号：US4961013A

公开(公告)日：1990-10-02

申请号：US423306

申请日：1989-10-18

申请人： John R. Obermeyer, Jr. ,  John F. Shelton ,  Donald A. Williamson

发明人： John R. Obermeyer, Jr. ,  John F. Shelton ,  Donald A. Williamson

IPC分类号： G01R31/3185 ,  H03K5/15

CPC分类号： H03K5/15 ,  G01R31/318572

摘要： A scan testable circuit in a computer system is controlled by using a single scan clock and a fixed delay circuit to realize the required scan clocks and a required scan mode enable signal. The multiple signals are generated from a subset of signals supplied to the scan control signal generation circuit. System data and scan data are routed through a multiplexer to test or initialize lines and circuitry. A scan control signal generation circuit according to the invention has the advantage of eliminating as excess a scan mode enable signal originating elsewhere in the computer system, thereby eliminating unneeded signal traces while minimizing the number of pins required for this function. In a first embodiment, a scan mode enable signal is generated from one of two scan clocks. In a second embodiment, both scan clocks and the scan mode enable signal are generated from a single source clock.

摘要翻译： 通过使用单个扫描时钟和固定延迟电路来控制计算机系统中的扫描可测试电路，以实现所需的扫描时钟和所需的扫描模式使能信号。 多个信号从提供给扫描控制信号发生电路的信号的子集产生。 系统数据和扫描数据通过多路复用器进行路由，以测试或初始化线路和电路。 根据本发明的扫描控制信号产生电路具有消除作为多余的源自计算机系统其他地方的扫描模式使能信号的优点，从而消除了不需要的信号迹线，同时使该功能所需的引脚数量最小化。 在第一实施例中，从两个扫描时钟之一产生扫描模式使能信号。 在第二实施例中，从单个源时钟产生扫描时钟和扫描模式使能信号。

公开(公告)号：US4635188A

公开(公告)日：1987-01-06

申请号：US518609

申请日：1983-07-29

申请人： Donald A. Williamson ,  John F. Shelton

发明人： Donald A. Williamson ,  John F. Shelton

IPC分类号： G06F9/26 ,  G06F9/30 ,  G06F9/318 ,  G06F9/22

CPC分类号： G06F9/30145 ,  G06F9/268 ,  G06F9/3017 ,  G06F9/3889

摘要： A scheme for improving the decoding time of macroinstruction opcodes in a programmed computer is provided. By having a direct Instruction Jump Table responding to macroinstructions and a pipelined Address Jump Table responding to the same macroinstructions simultaneously, larger sequences of microinstructions are decoded in a minimum number of microcycles, thus resulting in a faster operating programmed computer.

摘要翻译： 提供了一种用于改善编程计算机中的宏指令操作码的解码时间的方案。 通过具有响应宏指令的直接指令跳转表和同时响应相同宏指令的流水线地址跳转表，较大序列的微指令以最小数量的微循环被解码，从而导致更快的操作编程计算机。

公开(公告)号：US5708801A

公开(公告)日：1998-01-13

申请号：US744387

申请日：1996-11-07

申请人： James B. Williams ,  Kenneth K. Chan ,  John F. Shelton ,  Ehsan Rashid

发明人： James B. Williams ,  Kenneth K. Chan ,  John F. Shelton ,  Ehsan Rashid

IPC分类号： G06F1/06 ,  G06F13/42 ,  G06F1/12

CPC分类号： G06F1/06 ,  G06F13/4217

摘要： A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with the data bus at a second clock frequency. The system includes a clock generator for generating a bus clock signal at the first clock frequency and a chip clock signal at the second clock frequency wherein the first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein the bus and chip clock signals are synchronized once every N cycles of the chip clock signal. The clock generator also generates a synchronization signal indicating the chip clock signal cycle in which the bus and chip clock signals are synchronized. The circuit block includes an interface circuit for receiving and transmitting data on the bus. The system also includes circuits connected to each circuit block for identifying a chip clock signal cycle in which data cannot be transmitted by the circuit block on the bus and a chip clock signal cycle in which data cannot be received by the circuit block from the bus, there being one of each type of cycle in each contiguous block of N chip clock cycles.

摘要翻译： 一种数据通信系统，用于在以第一时钟频率运行的总线与在第二时钟频率与数据总线同步工作的电路块之间传送数据。 该系统包括用于产生第一时钟频率的总线时钟信号和第二时钟频率的芯片时钟信号的时钟发生器，其中第一和第二时钟信号频率的比率为（N-1）：N，其中N是 大于1的整数，并且其中总线和芯片时钟信号每芯片时钟信号的N个周期被同步一次。 时钟发生器还产生指示芯片时钟信号周期的同步信号，其中总线和芯片时钟信号同步。 电路块包括用于在总线上接收和发送数据的接口电路。 该系统还包括连接到每个电路块的电路，用于识别芯片时钟信号周期，其中数据不能由总线上的电路块发送，并且芯片时钟信号周期中，电路块不能从总线接收数据， 在N个芯片时钟周期的每个相邻块中存在每种类型的周期中的一种。

公开(公告)号：US5600824A

公开(公告)日：1997-02-04

申请号：US191865

申请日：1994-02-04

申请人： James B. Williams ,  Kenneth K. Chan ,  John F. Shelton ,  Ehsan Rashid

发明人： James B. Williams ,  Kenneth K. Chan ,  John F. Shelton ,  Ehsan Rashid

IPC分类号： G06F1/06 ,  G06F13/42 ,  G06F1/04

CPC分类号： G06F1/06 ,  G06F13/4217

摘要： A data communication system for communicating data between a bus running at a first clock frequency and a circuit block operating synchronously with the data bus at a second clock frequency. The system includes a clock generator for generating a bus clock signal at the first clock frequency and a chip clock signal at the second clock frequency wherein the first and second clock signal frequencies are in the ratio of (N-1):N where N is an integer greater than 1 and wherein the bus and chip clock signals are synchronized once every N cycles of the chip clock signal. The clock generator also generates a synchronization signal indicating the chip clock signal cycle in which the bus and chip clock signals are synchronized. The circuit block includes an interface circuit for receiving and transmitting data on the bus. The system also includes circuits connected to each circuit block for identifying a chip clock signal cycle in which data cannot be transmitted by the circuit block on the bus and a chip clock signal cycle in which data cannot be received by the circuit block from the bus, there being one of each type of cycle in each contiguous block of N chip clock cycles.

摘要翻译： 一种数据通信系统，用于在以第一时钟频率运行的总线与在第二时钟频率与数据总线同步工作的电路块之间传送数据。 该系统包括用于产生第一时钟频率的总线时钟信号和第二时钟频率的芯片时钟信号的时钟发生器，其中第一和第二时钟信号频率的比率为（N-1）：N，其中N为 大于1的整数，并且其中总线和芯片时钟信号每芯片时钟信号的N个周期被同步一次。 时钟发生器还产生指示芯片时钟信号周期的同步信号，其中总线和芯片时钟信号同步。 电路块包括用于在总线上接收和发送数据的接口电路。 该系统还包括连接到每个电路块的电路，用于识别芯片时钟信号周期，其中数据不能由总线上的电路块发送，并且芯片时钟信号周期中，电路块不能从总线接收数据， 在N个芯片时钟周期的每个相邻块中存在每种类型的周期中的一种。

公开(公告)号：US5091851A

公开(公告)日：1992-02-25

申请号：US382158

申请日：1989-07-19

申请人： John F. Shelton ,  Richard J. Carter

发明人： John F. Shelton ,  Richard J. Carter

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0864 ,  G06F12/0886

摘要： A multi-way set-associative cache memory stores data in a plurality of random access memories. Data in the multi-way set-associative cache memory is organized in lines of data. The multi-way set-associative cache memory allows access of single words and allows access of multiple-words of a length specific to the multi-way set-associative cache memory. Within the plurality of random access memories, data are placed such that corresponding words of each line of data is placed in different random access memories. Further, each word from each multiple word is placed in different random access memories. For single word access, one word is accessed from one of the plurality of random access memories. For multiple-word access, one word from each of the plurality of random access memories is accessed.

公开(公告)号：US5155828A

公开(公告)日：1992-10-13

申请号：US810523

申请日：1991-12-17

申请人： Ross V. La Fetra ,  John F. Shelton

发明人： Ross V. La Fetra ,  John F. Shelton

IPC分类号： G06F12/08

CPC分类号： G06F12/0897

摘要： A computing system includes a processor, a system memory containing data utilized by the processor and two cache memories. Each cache memory is connected directly to the processor. A first cache memory is connected to the processor and to the system memory. The first cache memory contains a subset of data in the system memory. A second cache memory is also connected to the processor. The second cache memory contains a subset of data in the first cache memory. Data integrity in the system memory is maintained using the first cache memory only. Whenever the processor writes data, the processor writes data both to the first cache memory and to the second cache memory. Whenever the processor reads data, the processor attempts to read data from the second cache memory. If there is a miss at the second cache memory, the processor attempts to read data from the first cache memory. If there is a miss at the first cache memory, the data is retrieved from the system memory and placed in the first cache memory. The processor then reads the data from the first cache memory. Generally, when the processor reads data from the first cache memory, the read data is written into the second cache memory.

摘要翻译： 计算系统包括处理器，包含由处理器使用的数据和两个高速缓冲存储器的系统存储器。 每个缓存存储器直接连接到处理器。 第一缓存存储器连接到处理器和系统存储器。 第一个缓存存储器包含系统内存中的数据子集。 第二高速缓存存储器也连接到处理器。 第二缓存存储器包含第一高速缓冲存储器中的数据子集。 仅使用第一个高速缓冲存储器来维护系统内存中的数据完整性。 每当处理器写入数据时，处理器将数据都写入第一高速缓冲存储器和第二高速缓冲存储器。 每当处理器读取数据时，处理器尝试从第二高速缓冲存储器读取数据。 如果在第二高速缓存存储器中存在未命中，则处理器尝试从第一高速缓冲存储器读取数据。 如果在第一缓存存储器中存在缺失，则从系统存储器检索数据并将其放置在第一缓存存储器中。 然后处理器从第一高速缓冲存储器读取数据。 通常，当处理器从第一高速缓冲存储器读取数据时，将读取的数据写入第二高速缓冲存储器。