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19 条记录 (耗时 0.032 秒)

    Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus
    1.
    发明授权
    Multiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the bus 失效
    通过按照在总线上发出的事务的顺序检查一致性来维持高速缓存一致性的多处理器系统

    公开(公告)号：US5530933A

    公开(公告)日：1996-06-25

    申请号：US201463

    申请日：1994-02-24

    申请人： Craig R. Frink ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert D. Odineal ,  James B. Williams ,  Michael L. Ziegler

    发明人： Craig R. Frink ,  William R. Bryg ,  Kenneth K. Chan ,  Thomas R. Hotchkiss ,  Robert D. Odineal ,  James B. Williams ,  Michael L. Ziegler

    IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/06

    CPC分类号： G06F12/0831

    摘要： A coherency scheme of use with a system having a bus, a main memory, a main memory controller for accessing main memory in response to transactions received on the bus, and a set of processor modules coupled to the bus. Each processor module has a cache memory and is capable of transmitting coherent transactions on the bus to other processor modules and to the main memory controller. Each processor module detects coherent transactions issued on the bus and performs cache coherency checks for each of the coherent transactions. Each processor module has a coherency queue for storing all transactions issued on the bus and for performing coherency checks for the transactions in first-in, first-out order. When a module transmits a coherent transaction on a bus, it places its own transaction into its own coherency queue.

    摘要翻译： 与具有总线的系统一起使用的一致性方案，主存储器，用于响应于在总线上接收到的事务来访问主存储器的主存储器控制器，以及耦合到总线的一组处理器模块。 每个处理器模块具有高速缓冲存储器，并且能够将总线上的相干事务发送到其他处理器模块和主存储器控制器。 每个处理器模块检测总线上发出的相干事务，并执行每个相干事务的高速缓存一致性检查。 每个处理器模块具有用于存储在总线上发布的所有事务的一致性队列，并且用于以先入先出顺序执行事务的一致性检查。 当模块在总线上传输一致的事务时，它将自己的事务置于自己的一致性队列中。

    Atomic operation control scheme
    4.
    发明授权
    Atomic operation control scheme 失效
    原子操作控制方案

    公开(公告)号：US5586274A

    公开(公告)日：1996-12-17

    申请号：US217687

    申请日：1994-03-24

    申请人： William R. Bryg ,  Craig R. Frink ,  Larry N. McMahan ,  Helen Nusbaum

    发明人： William R. Bryg ,  Craig R. Frink ,  Larry N. McMahan ,  Helen Nusbaum

    IPC分类号： G06F12/08 ,  G06F13/18 ,  G06F13/36 ,  G06F13/00

    CPC分类号： G06F13/36

    摘要： A split transaction bus system that accommodates atomic operations without locking the bus and without the possibility of deadlock during the atomic operations. The bus system may be used in a computer system that includes a bus, component modules that send transactions to each other on the bus, and a bus controller that limits the types of transactions that can be sent on the bus at any given time. When one module is performing an atomic operation, the bus controller limits transactions to those that do not change the memory image that existed when the atomic operation was commenced. The bus controller, however, permits responses or returns of data, assuming the response or return does not alter the current value of data.

    摘要翻译： 一种拆分事务总线系统，可以在不锁定总线的情况下适应原子操作，并且在原子操作期间不存在死锁的可能性。 总线系统可以用于包括总线，在总线上彼此发送事务的组件模块的总线控制器的总线控制器，该总线控制器限制在任何给定时间可以在总线上发送的事务的类型。 当一个模块执行原子操作时，总线控制器将事务限制为不改变原子操作开始时存在的存储器映像的事务。 但是，总线控制器允许响应或返回数据，假设响应或返回不会改变当前的数据值。

    Apparatus and method for controlling transfer of data between and processing of data by interconnected data processing elements
    5.
    发明授权
    Apparatus and method for controlling transfer of data between and processing of data by interconnected data processing elements 失效
    用于通过互连的数据处理元件来控制数据传输和数据处理之间的装置和方法

    公开(公告)号：US6105083A

    公开(公告)日：2000-08-15

    申请号：US879981

    申请日：1997-06-20

    申请人： Jeffrey D. Kurtze ,  Craig R. Frink ,  James Hamilton ,  Frank C. Sarnowski ,  Raymond D. Cacciatore ,  Scott A. Markinson ,  Michael F. Lamenza ,  Anthony O'Connor ,  Hamed Eshraghian

    发明人： Jeffrey D. Kurtze ,  Craig R. Frink ,  James Hamilton ,  Frank C. Sarnowski ,  Raymond D. Cacciatore ,  Scott A. Markinson ,  Michael F. Lamenza ,  Anthony O'Connor ,  Hamed Eshraghian

    IPC分类号： G06F13/38 ,  G06F13/42 ,  H04N7/24 ,  H04N7/26 ,  H04N7/50

    CPC分类号： G06F13/4213 ,  H04N19/42 ,  H04N19/61 ,  H04N7/24

    摘要： The present invention provides a generic interface which enables asynchronous data processing elements to be interconnected using an interconnection protocol that controls flow of data between the processing elements. The flow control allows the processing elements to be data independent from, i.e., the processing elements need not be designed for a fixed sample rate or resolution, sample format and other data dependent factors. When used with digital motion video data, the processing elements may process motion video data at various temporal and spatial resolutions and color formats. Flow of data between processing elements may be controlled by handshake signals indicating whether the sender has valid data and the receiver can receive data. When valid data is available at the sender and is requested by the receiver, a transfer of data occurs. The characteristics of the data, and functions to be performed on the data may be specified using control inputs to the processing elements. A counting circuit may be used to specify the number of the data samples for which the control inputs are valid. The interface allows each processing element to have a small number of storage locations for storing data, such as a pair of registers, which eliminates the need for large buffers and simplifies implementation of the processing element with such flow control as a simple integrated circuit.

    摘要翻译： 本发明提供了一种通用接口，其使得能够使用控制处理元件之间的数据流的互连协议来互连异步数据处理元件。 流量控制允许处理元件与数据无关，即处理元件不需要被设计用于固定的采样率或分辨率，采样格式和其他依赖于数据的因素。 当与数字运动视频数据一起使用时，处理元件可以处理各种时间和空间分辨率和颜色格式的运动视频数据。 处理元件之间的数据流可以由指示发送者是否具有有效数据并且接收方可以接收数据的握手信号来控制。 当有效数据在发送器处可用并且被接收器请求时，发生数据传送。 可以使用对处理元件的控制输入来指定数据的特性和对数据执行的功能。 可以使用计数电路来指定控制输入有效的数据样本的数量。 该接口允许每个处理元件具有用于存储数据的少量存储位置，诸如一对寄存器，其消除了对大缓冲器的需要并且简化了具有如简单集成电路的流量控制的处理元件的实现。

    Hierarchical shaping of network traffic
    6.
    发明授权
    Hierarchical shaping of network traffic 有权
    网络流量的分层整形

    公开(公告)号：US09031079B1

    公开(公告)日：2015-05-12

    申请号：US10912041

    申请日：2004-08-06

    申请人： Craig R. Frink

    发明人： Craig R. Frink

    IPC分类号： H04L12/28 ,  H04L12/26

    CPC分类号： H04L47/22 ,  H04J3/247 ,  H04L12/5601 ,  H04L43/062 ,  H04L47/50 ,  H04L47/568 ,  H04L47/6205 ,  H04L49/254 ,  H04L49/3081 ,  H04L49/9005 ,  H04L2012/568

    摘要： Stacked (i.e., hierarchically arranged) rate wheels schedule traffic flows in a network. A first rate wheel operates to efficiently schedule traffic flows in which traffic shaping parameters may be applied to individual traffic flows. A second rate wheel schedules group of the traffic flows in which traffic shaping parameters may be applied at the group level. In the context of an ATM network, the first rate wheel may operate at the virtual circuit level and the second rate wheel may operate at the virtual path level.

    摘要翻译： 堆叠（即，分层布置）速率轮调度网络中的业务流。 第一速率轮操作以有效地调度可以将流量整形参数应用于个体业务流的业务流。 第二速率轮调度可以在组级别应用流量整形参数的业务流的组。 在ATM网络的上下文中，第一速率轮可以在虚拟电路级操作，并且第二速率轮可以在虚拟路径级别操作。

    Collision compensation in a scheduling system
    8.
    发明授权
    Collision compensation in a scheduling system 有权
    调度系统中的碰撞补偿

    公开(公告)号：US07457247B1

    公开(公告)日：2008-11-25

    申请号：US10876625

    申请日：2004-06-28

    申请人： Craig R. Frink

    发明人： Craig R. Frink

    IPC分类号： G06F11/00 ,  G06F15/16

    CPC分类号： H04L47/6205 ,  H04L12/5601 ,  H04L47/50 ,  H04L47/568 ,  H04L49/3081 ,  H04L2012/5652 ,  H04L2012/5679 ,  H04L2012/5681

    摘要： A system schedules traffic flows on an output port using a circular memory structure. The circular memory structure may be a rate wheel that includes a group of sequentially arranged slots. The rate wheel schedules the traffic flows in select ones of the slots based on traffic shaping parameters assigned to the flows. The rate wheel compensates for collisions between multiple flows that occur in the slots by subsequently skipping empty slots.

    摘要翻译： 系统使用循环存储器结构在输出端口上调度流量。 循环存储器结构可以是包括一组顺序排列的槽的速率轮。 速率轮根据分配给流量的流量整形参数来调度某些时隙中的流量。 速率轮通过随后跳过空槽来补偿在槽中发生的多个流之间的冲突。

    HDTV editing and effects previsualization using SDTV devices
    9.
    发明授权
    HDTV editing and effects previsualization using SDTV devices 失效
    HDTV编辑和使用SDTV设备进行预视化

    公开(公告)号：US06678002B2

    公开(公告)日：2004-01-13

    申请号：US09800883

    申请日：2001-03-07

    申请人： Craig R. Frink ,  Raymond Cacciatoro

    发明人： Craig R. Frink ,  Raymond Cacciatoro

    IPC分类号： H04N701

    CPC分类号： H04N5/262 ,  G11B27/034 ,  G11B2220/415

    摘要： A system provides real-time previsualization of effects to be added to high definition (HD) video data and real-time rendering of the HD video data including the added effects. The computer based system for editing high definition television (HDTV) resolution video includes a high definition video system connected to a standard definition video system and a high definition storage system. A resizer reformats the high definition video data to standard definition resolution for real-time processing and previsualization.

    摘要翻译： 系统提供对要添加到高分辨率（HD）视频数据的效果的实时预先查看，以及包括添加的效果的HD视频数据的实时渲染。 用于编辑高分辨率电视（HDTV）分辨率视频的基于计算机的系统包括连接到标准清晰度视频系统和高清晰度存储系统的高清晰度视频系统。 调整器将高分辨率视频数据重新格式化为标准清晰度分辨率，用于实时处理和预视。

    Editing system with router for connection to HDTV circuitry
    10.
    发明授权
    Editing system with router for connection to HDTV circuitry 失效

    公开(公告)号：US07046251B2

    公开(公告)日：2006-05-16

    申请号：US10375599

    申请日：2003-02-27

    申请人： Morton Tarr ,  Peter Fasciano ,  Craig R. Frink

    发明人： Morton Tarr ,  Peter Fasciano ,  Craig R. Frink

    IPC分类号： H04N5/14

    CPC分类号： G11B27/034 ,  H04N5/262

    摘要： A non-linear editor is connected to video processing equipment through a serial digital video interface to edit high definition (HD) television video data. The non-linear editor includes a randomly accessible, computer-readable and re-writeable storage medium that stores a plurality of sequences of HD digital images representing a frame or field of HD motion video data. The non-linear editor provides a configuration control signal to identify processing to be performed on the HD video data and defines a video program to be rendered using the stored HD digital images. An input serial digital interface and an output serial digital interface in the non-linear editor provide the HD video data to be edited. A multiformat video router controls the HD video data sent between the non-linear editor and the video processing equipment. The router is video interconnected to the video processing equipment and to the serial digital interfaces of the non-linear editor.