公开(公告)号：US06403494B1

公开(公告)日：2002-06-11

申请号：US09638300

申请日：2000-08-14

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Jack Yeh ,  Chia-Ta Hsieh ,  Chuan-Li Chang

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Jack Yeh ,  Chia-Ta Hsieh ,  Chuan-Li Chang

IPC分类号： H01L2100

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to a shallow trench isolation (STI), which in turn makes it self-aligned to source and to word line. This will advantageously affect a shrinkage in the size of the memory cell. In a first embodiment, the close self-alignment is made possible through a new use of an anti-reflective coating (ARC) in the various process steps of the making of the cell. In the second embodiment, a low-viscosity material is used in such a manner so as to enable self-alignment of the floating gate to the STI in a simple way.

摘要翻译： 公开了一种用于形成分裂栅极闪存单元的方法，其中单元的浮置栅极自对准到浅沟槽隔离（STI），其又使得其自对准到源极和字线。 这将有利地影响存储器单元的尺寸的收缩。 在第一实施例中，通过在制造电池的各种工艺步骤中新的使用抗反射涂层（ARC）使得紧密的自对准成为可能。 在第二实施例中，以这样的方式使用低粘度材料，以便能够以简单的方式使浮动栅极与STI的自对准。

公开(公告)号：US06312989B1

公开(公告)日：2001-11-06

申请号：US09489496

申请日：2000-01-21

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Wen-Ting Chu ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell. The vertical orientation of the source structure and the floating gate and the self-alignment of the spacer control gate to the floating gate together makes it possible to reduce the memory cell substantially.

摘要翻译： 公开了一种用于形成具有突出源的分裂栅极闪存单元来代替常规扁平源的方法。 垂直突出的源结构具有顶部和底部。 底部是多晶硅，而顶部是多晶氧化物。 源极上的突出结构的垂直壁用于形成具有中间栅极氧化物的垂直浮动栅极和间隔物控制栅极。 因为现在通过垂直壁提供源极和浮动栅极之间的耦合，所以耦合面积比常规扁平源大得多。 此外，不再存在源极和漏极之间的电压穿通的问题。 垂直浮动栅极也变薄，使得所得到的薄而尖锐的多尖端进一步增强了闪存单元的擦除和编程速度。 源结构和浮置栅极的垂直取向以及间隔物控制栅极与浮置栅极的自对准一起使得可以基本上减小存储单元。

公开(公告)号：US06245685B1

公开(公告)日：2001-06-12

申请号：US09387441

申请日：1999-09-01

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh

IPC分类号： H01L2100

CPC分类号： H01L27/11521 ,  H01L21/28114 ,  H01L21/28123 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/823842 ,  H01L27/115

摘要： A method for forming a square oxide structure or a square floating gate without a rounding effect at its corners. A first dielectric layer is formed on a pad layer for a square oxide structure or a polysilicon layer overlying a gate oxide layer for a floating gate, and a second dielectric layer is formed on the first dielectric layer. The second dielectric layer is patterned to form parallel openings in a first direction using a first photosensitive mask. A second photosensitive mask, having a plurality of parallel openings in a second direction perpendicular to the first direction is formed over the second dielectric layer and the first dielectric layer. The first dielectric layer is etched through square openings where the openings in the second photosensitive mask and the openings in the second dielectric layer intersect, thereby forming square openings in the first dielectric layer. The second photosensitive mask and the second dielectric layer are removed. The square oxide structure is completed by etching a trench in the semiconductor structure and forming an STI or LOCOS. The square floating gate is completed by growing polysilicon oxide structures in the square openings in the first dielectric layer and removing the first dielectric layer to form a pattern of openings therebetween, and etching the polysilicon layer through the pattern of openings between the polysilicon oxide structures forming square floating gate polysilicon regions under the polysilicon oxide hard masks.

摘要翻译： 用于在其角部形成平方氧化物结构或方形浮动栅极而不具有圆化效应的方法。 第一电介质层形成在用于平面氧化物结构的焊盘层或覆盖用于浮置栅极的栅极氧化物层的多晶硅层上，并且第二介电层形成在第一介电层上。 图案化第二电介质层以使用第一感光掩模在第一方向上形成平行的开口。 在第二电介质层和第一电介质层上形成第二光敏掩模，在与第一方向垂直的第二方向上具有多个平行的开口。 通过正方形开口蚀刻第一电介质层，其中第二感光掩模中的开口和第二介电层中的开口相交，从而在第一介电层中形成方形开口。 去除第二光敏掩模和第二介电层。 通过蚀刻半导体结构中的沟槽并形成STI或LOCOS来完成平方氧化物结构。 通过在第一电介质层的正方形开口中生长多晶氧化物结构并去除第一电介质层以形成其间的开口图案来完成正方形浮栅，并且通过形成多晶硅氧化物结构之间的开口图案蚀刻多晶硅层 方形浮栅多晶硅区域下的多晶硅氧化物硬掩模。

公开(公告)号：US6130132A

公开(公告)日：2000-10-10

申请号：US55439

申请日：1998-04-06

申请人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L27/11521 ,  H01L21/28273

摘要： The following steps are used to form a split gate electrode MOS FET device. Form a tunnel oxide layer over a semiconductor substrate. Over the tunnel oxide layer, form a doped first polysilicon layer with a top surface upon which a native oxide forms. Then as an option, remove the native oxide layer. On the top surface of the first polysilicon layer, form a silicon nitride layer and etch the silicon nitride layer to form it into a cell-defining layer. Form a polysilicon oxide dielectric cap over the top surface of the first polysilicon layer. Aside from the polysilicon oxide cap, etch the first polysilicon layer and the tunnel oxide layer to form a floating gate electrode stack in the pattern of the masking cap forming a sharp peak on the periphery of the floating gate electrode. Form spacers on the sidewalls of the gate electrode stack. Then form blanket inter-polysilicon dielectric and blanket control gate layers covering exposed portions of the substrate and covering the stack. Pattern the inter-polysilicon dielectric and control gate layers into a split gate electrode pair. Form a source region self-aligned with the floating gate electrode stack; perform a tungsten silicide anneal; and form a drain region self-aligned with the control gate electrodes.

摘要翻译： 以下步骤用于形成分离栅电极MOS FET器件。 在半导体衬底上形成隧道氧化层。 在隧道氧化物层上形成掺杂的第一多晶硅层，其上形成有天然氧化物的顶表面。 然后作为选项，删除自然氧化物层。 在第一多晶硅层的顶表面上，形成氮化硅层并蚀刻氮化硅层以形成单元限定层。 在第一多晶硅层的顶表面上形成多晶硅氧化物电介质盖。 除了多晶硅氧化物盖之外，蚀刻第一多晶硅层和隧道氧化物层以形成掩模帽图案中的浮栅电极堆叠，在浮栅电极的外围形成尖锐的峰。 在栅极电极堆叠的侧壁上形成间隔物。 然后形成覆盖基板的暴露部分并覆盖堆叠的覆盖层间多晶硅电介质和覆盖层控制栅极层。 将多晶硅间介质和控制栅极层图案化成分离栅电极对。 形成与浮栅电极堆叠自对准的源区; 进行硅化钨退火; 并形成与控制栅电极自对准的漏区。

公开(公告)号：US6127229A

公开(公告)日：2000-10-03

申请号：US301222

申请日：1999-04-29

申请人： Wen-Ting Chu ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Wen-Ting Chu ,  Di-Son Kuo ,  Hung-Cheng Sung ,  Jack Yeh ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521

摘要： There is presented an improved method of fabricating an EEPROM device with a split gate. In the method, a silicon substrate is provided having spaced and parallel recessed oxide regions that isolate component regions where the oxide regions project above the top surface of the substrate. A thin gate oxide is formed on the substrate, and a first conformal layer is deposited over the gate oxide and projecting oxide regions. The substrate is then chemical-mechanically polished to remove the projections of polysilicon over the oxide regions. A silicon nitride layer is deposited on the resultant planar surface of the polysilicon, and elongated openings formed that will define the position of the floating gates that are perpendicular to the oxide regions. The exposed polysilicon in the openings in the silicon nitride are oxidized down to at least the level of the underlying silicon oxide regions, and the silicon nitride layer removed. The polysilicon layer is then removed using the silicon oxide layer as an etch barrier, and the edge surfaces of the resulting polysilicon floating gates oxidized. A second polysilicon layer is deposited on the substrate and elongated word lines formed that are parallel and partially overlapping the floating gates. Source lines are formed in the substrate, and gate lines are formed that overlie the floating gates.

摘要翻译： 提出了一种用分裂栅极制造EEPROM器件的改进方法。 在该方法中，提供硅衬底，其具有间隔开且平行的凹陷氧化物区域，其隔离氧化物区域突出在衬底的顶表面上方的组分区域。 在衬底上形成薄栅氧化物，并且在栅极氧化物和突出的氧化物区域上沉积第一共形层。 然后将衬底进行化学机械抛光以去除多晶硅在氧化物区域上的突起。 在所形成的多晶硅的平坦表面上沉积氮化硅层，形成将形成垂直于氧化物区域的浮栅的位置的细长开口。 氮化硅中的开口中的暴露的多晶硅被氧化到至少下面的氧化硅区域的水平，并且去除了氮化硅层。 然后使用氧化硅层作为蚀刻阻挡层去除多晶硅层，并且所得多晶硅浮栅的边缘表面被氧化。 第二多晶硅层沉积在衬底上，并且形成平行且部分地与浮动栅极重叠的细长字线。 在衬底中形成源极线，并且形成覆盖浮栅的栅极线。

公开(公告)号：US6117733A

公开(公告)日：2000-09-12

申请号：US193670

申请日：1998-11-17

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： H01L21/8247 ,  H01L29/423 ,  H01L21/336 ,  H01L29/72 ,  H01L31/00

CPC分类号： H01L29/42324 ,  H01L27/11519 ,  H01L27/11521

摘要： A novel method of forming a first polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notch in two different ways in a nitride layer overlying the first polysilicon layer. In one embodiment, the notch is formed after wet oxidizing the sidewalls of the underlying first polysilicon layer, thus at the same time forming a poly tip which is exposed upwardly but covered by polyoxide on the side. In another embodiment, the notch is formed prior to the oxidation of the exposed regions of the first polysilicon layer, such as the sidewalls, so that during the subsequent oxidation, not only the sidewalls but also the exposed portions of the polysilicon in the notch region are also oxidized. Because the oxidation of the polysilicon advances in a non-uniform manner with very little at the polysilicon/nitride interface and to a larger rate elsewhere, a thin and robust polysilicon tip is formed which is at the same time covered by oval-shaped poly-oxide on all sides. A method of forming a self-aligned source (SAS) line is also disclosed in conjunction with the forming of the polytip. Hence the combination of an enhanced poly tip with a self-aligned source provides a faster split-gate flash memory device.

摘要翻译： 公开了一种用于形成分裂栅闪存单元中用于增强的F-N隧穿的第一多晶硅栅尖（多头）的新方法。 通过在覆盖第一多晶硅层的氮化物层中以两种不同的方式形成凹口来进一步增强多晶硅尖端。 在一个实施例中，凹陷是在湿氧化下面的第一多晶硅层的侧壁之后形成的，因此同时形成向上暴露但被侧面被多氧化物覆盖的多边尖端。 在另一个实施例中，在第一多晶硅层（例如侧壁）的暴露区域的氧化之前形成凹口，使得在随后的氧化期间，不仅侧壁而且在凹口区域中的多晶硅的暴露部分 也被氧化。 由于多晶硅的氧化以非均匀的方式在多晶硅/氮化物界面处以非常小的速度前进，并且在其它地方以更大的速率前进，形成了薄而坚固的多晶硅尖端，同时被椭圆形多晶硅/ 氧化物在所有方面。 结合形成聚丝片也公开了形成自对准源（SAS）线的方法。 因此，增强型多头尖端与自对准源的组合提供了更快的分离栅极闪存器件。

公开(公告)号：US6090668A

公开(公告)日：2000-07-18

申请号：US248725

申请日：1999-02-11

申请人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jung-Ke Yeh ,  Chang-Song Lin ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jung-Ke Yeh ,  Chang-Song Lin ,  Di-Son Kuo

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L29/423

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42324

摘要： A method is provided for forming a split-gate flash memory cell having a sharp poly tip which substantially improves the erase speed of the cell. The poly tip is formed without the need for conventional oxidation of the polysilicon floating gate. Instead, the polysilicon layer is etched using a high pressure recipe thereby forming a recess with a sloped profile into the polysilicon layer. The recess is filled with a top-oxide, which in turn serves as a hard mask in etching those portions of the polysilicon year not protected by the top-oxide layer. The edge of the polysilicon layer formed by the sloping walls of the recess forms the sharp poly tip of this invention. The sharp tip does not experience the damage caused by conventional poly oxidation processes and, therefore, provides enhanced erase speed for the split-gate flash memory cell. The invention is also directed to a semiconductor device fabricated by the disclosed method.

摘要翻译： 提供了一种用于形成具有尖锐多边尖端的分裂栅极闪存单元的方法，其基本上改善了单元的擦除速度。 形成多边形，而不需要多晶硅浮动栅极的常规氧化。 相反，使用高压配方蚀刻多晶硅层，从而形成具有倾斜轮廓的凹陷到多晶硅层中。 凹部填充有顶部氧化物，其又用作蚀刻多晶硅年份未被顶部氧化物层保护的那些部分的硬掩模。 由凹陷的倾斜壁形成的多晶硅层的边缘形成本发明的尖锐的多边形尖端。 锋利的尖端不会经历由常规聚氧化过程引起的损坏，因此为分离式闪存单元提供增强的擦除速度。 本发明还涉及通过所公开的方法制造的半导体器件。

公开(公告)号：US06468863B2

公开(公告)日：2002-10-22

申请号：US09761276

申请日：2001-01-16

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jake Yeh ,  Chuan-Li Chang ,  Wen-Ting Chu ,  Sheng-Wei Tsaur

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Jake Yeh ,  Chuan-Li Chang ,  Wen-Ting Chu ,  Sheng-Wei Tsaur

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： Within both a method for fabricating a split gate field effect transistor and the split gate field effect transistor fabricated employing the method, there is employed a patterned silicon nitride barrier dielectric layer formed covering a first portion of a floating gate and a first portion of a semiconductor substrate adjacent the first portion of the floating gate. Within the first portion of the semiconductor substrate there is eventually formed a source/drain region, and more particularly a source region, when fabricating the split gate field effect transistor. The patterned silicon nitride barrier dielectric layer inhibits when fabricating the split gate field effect transistor ion implant damage of the floating gate and oxidative loss of a floating gate electrode edge.

摘要翻译： 在制造分裂栅极场效应晶体管的方法和使用该方法制造的分裂栅极场效应晶体管的两者中，采用形成为覆盖浮置栅极的第一部分和半导体的第一部分的图案化氮化硅阻挡介电层 衬底邻近浮动栅极的第一部分。 在半导体衬底的第一部分内，当制造分裂栅极场效应晶体管时，最终形成源极/漏极区域，尤其是源极区域。 图案化的氮化硅阻挡介电层在制造分离栅场效应晶体管离子注入损坏浮栅和浮栅电极边缘的氧化损失时禁止。

公开(公告)号：US06355527B1

公开(公告)日：2002-03-12

申请号：US09314588

申请日：1999-05-19

申请人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Jack Yeh ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is provided for forming a split-gate flash memory cell having reduced size, increased coupling ratio and improved program speed. A split-gate cell is also provided where the a first polysilicon layer forms the floating gate disposed over an intervening intergate oxide formed over a second polysilicon layer forming the control gate. However, the second polysilicon layer is also formed over the source region and overlying the other otherwise exposed portion of the floating gate such that this additional poly line now shares the voltage between the source and the floating gate, thereby reducing punch-through and junction breakdown voltages. In addition, the presence of another poly wall along the floating gate increases the coupling ratio between the source and the floating gate, which in turn improves program speed of the split-gate flash memory cell.

摘要翻译： 提供了一种用于形成具有减小的尺寸，增加的耦合比和改进的程序速度的分离栅极闪存单元的方法。 还提供了分离栅极单元，其中第一多晶硅层形成布置在形成在形成控制栅极的第二多晶硅层上的中间栅极氧化物上的浮置栅极。 然而，第二多晶硅层也形成在源极区上方并且覆盖浮置栅极的另一个另外暴露的部分，使得该附加多线现在共享源极和浮置栅极之间的电压，从而减少穿通和结击穿 电压。 此外，沿浮置栅极的另一个多壁的存在增加了源极和浮置栅极之间的耦合比，这进而提高了分离栅极闪存单元的编程速度。

公开(公告)号：US06284596B1

公开(公告)日：2001-09-04

申请号：US09213453

申请日：1998-12-17

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an intervening intergate oxide layer, it is conventionally incompatible to form self-aligned silicides over the control gate due to its position at a different level from that of the floating gate. Furthermore, oxide spacers that are normally used are inadequate when applied to memory cells. It is shown in the present invention that by a judicious use of an additional nitride/oxide layer over the control gate, oxide spacers can now be used effectively to delineate areas on the control gate that can be silicided and also self-aligned. Hence, with this method, salicidation and self-aligned contact techniques can be used not only on the same VLSI and ULSI chips having both peripheral logic devices and memory devices, but also in memory devices themselves.

摘要翻译： 公开了一种用于形成具有盐化控制栅极和自对准触点的分离栅极闪存单元的方法。 通常用单栅极器件（例如逻辑器件）执行致敏。 在分支栅极中，其中控制栅极与中间栅极氧化物层覆盖浮置栅极，因为它们的位置与浮置栅极的位置处于不同的水平位置，因此在控制栅极上形成自对准硅化物是常规的不相容的。 此外，通常使用的氧化物间隔物在应用于存储单元时是不充分的。 在本发明中显示，通过在控制栅极上明智地使用另外的氮化物/氧化物层，现在可以有效地使用氧化物间隔物来描绘控制栅上可被硅化并且自对准的区域。 因此，利用这种方法，不仅可以使用具有外围逻辑器件和存储器件的同一VLSI和ULSI芯片，而且可以用于存储器件本身中，可以使用水化和自对准接触技术。