公开(公告)号：US06410957B1

公开(公告)日：2002-06-25

申请号：US09713840

申请日：2000-11-16

申请人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-Cheng Sung

发明人： Chia-Ta Hsieh ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-Cheng Sung

IPC分类号： H01L218247

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： A method is disclosed for forming a split gate flash memory cell having a thin floating gate and a sharp poly tip in order to improve the erasing and programming speed of the cell. The method involves the use of an oxide other than the poly oxide that is conventionally employed in forming the floating gate, and also using to advantage a so-called “smiling effect” which is normally taught away. The smiling effect, or an uneven thickening of an oxide layer, comes into play while growing interpoly oxide where concurrently the oxidation of the polysilicon gate advances in such a manner so as to form a sharp and reliable poly tip. The invention is also directed to providing a split gate flash memory cell having a thin floating gate and a poly tip therein.

摘要翻译： 公开了一种用于形成具有薄浮动栅极和尖锐多晶硅尖端的分裂栅极快闪存储器单元的方法，以便提高电池的擦除和编程速度。 该方法包括使用通常用于形成浮动栅极的多晶氧化物以外的氧化物，并且还利用通常被教导的所谓的“微笑效果”。 微生物效应或氧化物层的不均匀增厚在生长多晶氧化物的同时发生，同时多晶硅栅极的氧化同时进行以形成尖锐且可靠的多晶硅尖端。 本发明还涉及提供一种具有薄的浮动栅极和多个尖端的分裂栅极闪存单元。

公开(公告)号：US06326660B1

公开(公告)日：2001-12-04

申请号：US09524522

申请日：2000-03-13

申请人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  Y10S438/981

摘要： A method is provided for forming a split-gate flash memory cell having reduced size, increased capacitive coupling and improved data retention capability. A split gate cell is also provided with appropriate gate oxide thicknesses between the substrate and the floating gate and between the float gate and the control gate along with an extra thin nitride layer formed judiciously over the primary gate oxide layer in order to overcome the problems of low data retention capacity of the floating gate and the reduced capacitive coupling between the floating gate and the source of prior art.

摘要翻译： 提供了一种用于形成具有减小的尺寸，增加的电容耦合和改进的数据保持能力的分离栅极闪存单元的方法。 分离栅极单元还在衬底和浮动栅极之间以及浮动栅极和控制栅极之间提供适当的栅极氧化物厚度以及在主栅极氧化物层上明智地形成的额外的薄的氮化物层，以克服以下问题： 浮动栅极的低数据保持容量和浮动栅极与现有技术的源之间的减小的电容耦合。

公开(公告)号：US06214662B1

公开(公告)日：2001-04-10

申请号：US09609165

申请日：2000-07-03

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Chia-Ta Hsieh ,  Yai-Fen Lin

IPC分类号： H01L218242

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is provided for forming a source line self-aligned to adjacent transistor device. This is accomplished by a forming a self-aligned polysilicon as a source line in an opening formed in a doped polysilicon layer separated from the source line by a spacer. The alignment of the poly source line with the transistor is provided by employing still another thin polysilicon layer as a mask for etching the source opening in the doped polysilicon layer which already has an outside wall aligned with respect to the contact hole for the drain of the device. An additional spacer is provided between the outside wall of the doped poly and the drain contact.

摘要翻译： 提供一种用于形成与相邻晶体管器件自对准的源极线的方法。 这是通过在通过间隔物与源极线分离的掺杂多晶硅层中形成的开口中形成作为源极线的自对准多晶硅来实现的。 多源线与晶体管的对准通过采用另外的薄多晶硅层作为掩模来提供，用于蚀刻掺杂多晶硅层中的源极开口，已经具有相对于接触孔对准的外壁，用于漏极 设备。 在掺杂多晶硅和漏极触点的外壁之间提供了另外的间隔物。

公开(公告)号：US06207515B1

公开(公告)日：2001-03-27

申请号：US09085611

申请日：1998-05-27

申请人： Chia-Ta Hsieh ,  Jenn Tsao ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-Cheng Sung

发明人： Chia-Ta Hsieh ,  Jenn Tsao ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-Cheng Sung

IPC分类号： H01L21265

CPC分类号： H01L29/0847 ,  H01L21/76895 ,  H01L27/1052 ,  H01L27/112 ,  H01L29/0649 ,  H01L29/66636

摘要： A method is provided for forming buried source line in semiconductor devices. It is known in the art to form buried contacts on the surface of a semiconductor substrate. The present invention discloses a method of fabricating a semiconductor device, particularly a memory cell, having both the source region and the source line buried within the substrate. The source line is formed in a trench in the substrate over the source region. The trench walls are augmented with voltage anti-punch-through protection. The trench also provides the attendant advantages of extended sidewall area, smaller sheet resistance, and yet smaller cell area, therefore, smaller chip size, and faster access time as claimed in the embodiments of this invention. The buried source disclosed here is integrated with source line which is also buried within the substrate.

摘要翻译： 提供一种用于在半导体器件中形成掩埋源极线的方法。 在本领域中已知在半导体衬底的表面上形成掩埋触点。 本发明公开了一种制造半导体器件的方法，特别是具有埋入衬底内的源极区和源极线两者的存储单元。 源极线形成在源极区域上的衬底中的沟槽中。 沟槽壁增强了电压抗穿透保护。 沟槽还提供了延伸的侧壁区域，较小的薄层电阻以及更小的单元面积，因此，更小的芯片尺寸和更快的访问时间，如本发明的实施例所要求的优点。 这里公开的掩埋源与源极线集成，该源极线也被埋在衬底内。

公开(公告)号：US06171906B2

公开(公告)日：2001-01-09

申请号：US09379227

申请日：1999-08-23

申请人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Chuang-Ke Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Chuang-Ke Yeh ,  Di-Son Kuo

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A method is provided for forming a split-gate flash memory cell having a sharp beak of poly which substantially improves the programming erase speed of the cell. The sharp beak is formed through an extra and judicious wet etch of the polyoxide formed after the oxidation of the first polysilicon layer. The extra oxide dip causes the polyoxide to be removed peripherally thus forming a re-entrant cavity along the edge of the floating gate. The re-entrant beak is such that it does not get damaged during the subsequent process steps and is especially suited for cell sizes smaller than 0.35 micrometers.

摘要翻译： 提供了一种用于形成具有尖锐尖峰的分裂栅极闪存单元的方法，其大大改善了单元的编程擦除速度。 通过对第一多晶硅层的氧化后形成的多氧化物进行额外且明智的湿法蚀刻，形成尖锐的喙。 额外的氧化物浸渍导致周围地去除多氧化物，从而沿着浮动栅极的边缘形成重入腔。 再入口的喙使得在后续工艺步骤中不会损坏，特别适用于小于0.35微米的电池尺寸。

公开(公告)号：US6124609A

公开(公告)日：2000-09-26

申请号：US439369

申请日：1999-11-15

申请人： Chia-Ta Hsieh ,  Jenn Tsao ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-Cheng Sung

发明人： Chia-Ta Hsieh ,  Jenn Tsao ,  Di-Son Kuo ,  Yai-Fen Lin ,  Hung-Cheng Sung

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is provided for forming a split-gate flash memory cell having reduced size, partially buried source line, increased source coupling ratio, improved programmability, and overall enhanced performance. A split-gate cell is also provided with reduced size and improved performance. The source line is formed in a trench in the substrate over the source region. The trench walls provide increased source coupling and the absence of gate bird's beak with the trench together shrink the cell size. Programmability is also enhanced through more favorable hot electron injection though intergate oxide between the floating gate and the control gate.

摘要翻译： 提供了一种用于形成具有减小的尺寸，部分埋入的源极线，增加的源耦合比，改进的可编程性和整体增强性能的分裂栅极快闪存储器单元的方法。 分裂门电池还具有减小的尺寸和改进的性能。 源极线形成在源极区域上的衬底中的沟槽中。 沟槽壁提供增加的源耦合，并且没有门鸟的喙与沟槽一起收缩细胞尺寸。 通过浮动栅极和控制栅极之间的隔间氧化物，通过更有利的热电子注入也可以提高可编程性。

公开(公告)号：US5972753A

公开(公告)日：1999-10-26

申请号：US984842

申请日：1997-12-04

申请人： Yai-Fen Lin ,  Hung-Cheng Sung ,  Chia-Ta Hsieh ,  Di-Son Kuo

发明人： Yai-Fen Lin ,  Hung-Cheng Sung ,  Chia-Ta Hsieh ,  Di-Son Kuo

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A method is provided for fabricating a self-aligned edge implanted split-gate flash memory comprising a semiconductor substrate of a first conductivity type having separated first and second regions of a second conductivity type formed therein, the first and second regions defining a substrate channel region therebetween; a floating gate separated from a doped region in the substrate by an oxide layer; a control gate partially overlying and separated by an insulator from said floating gate; said floating gate having thin portions and thick portions; and said thin portions of said floating gate overlying twice doped regions said semiconductor substrate to reduce surface leakage current and improve program speed of the memory cell.

摘要翻译： 提供了一种用于制造自对准边缘注入分裂栅极闪存的方法，该闪存包括形成有分离的第二和第二区域的第一导电类型的半导体衬底，第一和第二区域限定衬底沟道区域 之间; 通过氧化物层与衬底中的掺杂区域分离的浮置栅极; 由所述浮动栅极部分地由绝缘体覆盖并分离的控制栅极; 所述浮栅具有薄部分和厚部分; 并且所述浮动栅极的所述薄部分覆盖两个掺杂区域的所述半导体衬底，以减少表面泄漏电流并提高存储器单元的编程速度。

公开(公告)号：US5940706A

公开(公告)日：1999-08-17

申请号：US988764

申请日：1997-12-11

申请人： Hung-Cheng Sung ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chia-Ta Hsieh

发明人： Hung-Cheng Sung ,  Di-Son Kuo ,  Yai-Fen Lin ,  Chia-Ta Hsieh

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A select transistor for flash memory cells is made by the following steps. Over the blanket second dielectric layer, and an oxynitride layer form a channel mask for patterning the drain and floating gate. Etch the oxynitride layer through the mask to form a channel alignment mask down to a silicon nitride layer with a drain region opening and a floating gate opening. Etch the floating gate opening through the second dielectric layer. Form a polyoxide region in the floating gate layer at the bottom of the floating gate opening by reacting the exposed portion of the floating gate layer with a reactant. Form a drain region in the substrate. Etch away the oxynitride layer and the silicon nitride layer. Pattern the floating gate electrode by etching away the floating gate layer except below the polyoxide region. Form an interelectrode dielectric layer and a second gate electrode layer over the drain region and a portion of the polyoxide region. Form a source region in the substrate self-aligned with the polyoxide region.

摘要翻译： 用于闪存单元的选择晶体管通过以下步骤进行。 在整个第二介电层上，并且氧氮化物层形成用于图案化漏极和浮置栅极的沟道掩模。 通过掩模蚀刻氧氮化物层以形成通道对准掩模，直到具有漏极区域开口和浮动开口的氮化硅层。 通过第二介电层蚀刻浮动开口。 通过使浮栅的暴露部分与反应物反应，在浮动栅极开口底部的浮栅中形成多氧化物区域。 在衬底中形成漏区。 蚀刻掉氧氮化物层和氮化硅层。 通过蚀刻除了多晶氧化物区域之外的浮栅层来对浮栅电极进行图案化。 在漏极区域和一部分多氧化物区域上形成电极间电介质层和第二栅电极层。 在与氧化物区域自对准的衬底中形成源区。

公开(公告)号：US5879992A

公开(公告)日：1999-03-09

申请号：US115719

申请日：1998-07-15

申请人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Yai-Fen Lin ,  Hung-Cheng Sung ,  Chuang-Ke Yeh ,  Di-Son Kuo

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L21/8427

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched to form a step adjacent to the side-wall of a floating gate underlying the polyoxide. A spacer is next formed of a hot temperature oxide over the step poly. An interpoly oxynitride is then formed and control gate is patterned overlapping the floating gate with the intervening interpoly oxide. The step poly and the spacer thereon form proper distances between the control gate and the floating gate while keeping the distance between the poly tip and the control gate unchanged so that appropriate couplings between the control gate and the floating gate, and between the floating gate and the substrate are achieved, thus improving the over-all performance of the split-gate flash memory having a step poly.

摘要翻译： 提供了一种用于形成分支栅极快闪存储器单元的方法，其具有支撑不同厚度的多晶硅氧化物的台阶聚合物，以改善电池的全部性能。 多晶氧化物形成在第一多晶硅层的部分上，该第一多晶硅层又被部分蚀刻以形成邻近聚氧化物下面的浮动栅极的侧壁的台阶。 接着在步骤poly上由热的温度氧化物形成间隔物。 然后形成间极氧氮化物，并且控制栅极被图案化与浮置栅极与介入的多晶硅氧化物重叠。 步进多晶硅和间隔件在控制栅极和浮动栅极之间形成适当的距离，同时保持多晶硅尖端和控制栅极之间的距离不变，使得控制栅极和浮动栅极之间以及浮动栅极和浮动栅极之间的适当耦合 实现了衬底，从而改进了具有阶梯聚光的分离栅极闪存的全部性能。

公开(公告)号：US5858840A

公开(公告)日：1999-01-12

申请号：US995341

申请日：1997-12-22

申请人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Hung-Cheng Sung ,  Yai-Fen Lin ,  Di-Son Kuo

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L21/82

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A method is provided for forming a short and sharp gate bird's beak in order to increase the erase speed of a split-gate flash memory cell. This is accomplished by implanting nitrogen ions in the first polysilicon layer of the cell and removing them from the area where the floating gate is to be formed. Then, when the polysilicon layer is oxidized to form polyoxide, the floating gate region without the nitrogen ions oxidizes faster than the surrounding area still having the nitrogen ions. Consequently, the bird's beak that is formed at the edges of the polyoxide assumes a sharper shape with smaller size than that is found in prior art. This results in an increase in the erase speed of the memory cell.

摘要翻译： 提供了一种用于形成短而尖锐的门鸟喙的方法，以便增加分闸式闪存单元的擦除速度。 这是通过将氮离子注入到电池的第一多晶硅层中并将其从要形成浮栅的区域中去除来实现的。 然后，当多晶硅层被氧化形成聚氧化物时，没有氮离子的浮栅区域比仍然具有氮离子的周围区域更快地氧化。 因此，形成在多氧化物边缘的鸟嘴形状比现有技术中发现的具有更小的形状。 这导致存储单元的擦除速度的增加。