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46 条记录 (耗时 0.029 秒)

    Multiple gate field effect transistor structure
    41.
    发明申请
    Multiple gate field effect transistor structure 有权
    多栅场效应晶体管结构

    公开(公告)号：US20060180854A1

    公开(公告)日：2006-08-17

    申请号：US11057423

    申请日：2005-02-14

    申请人： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Hun-Jan Tao ,  Chang-Yun Chang ,  Zhong Xuan ,  Sheng-Da Liu

    发明人： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Hun-Jan Tao ,  Chang-Yun Chang ,  Zhong Xuan ,  Sheng-Da Liu

    IPC分类号： H01L31/113

    CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/78687

    摘要： A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel spaced apart sidewall portions, each of said sidewall portions comprising major inner and outer surfaces and an upper surface; wherein, each of said surfaces comprises a surface for forming an overlying field effect transistor (FET).

    摘要翻译： 一种用于形成多达6个FET器件的多栅极区域FET器件及其形成方法，该器件包括多个鳍状结构，其包括设置在衬底上的半导体材料; 所述多个鳍状结构包括基本上平行的间隔开的侧壁部分，每个所述侧壁部分包括主要内表面和外表面以及上表面; 其中，每个所述表面包括用于形成上覆场效应晶体管（FET）的表面。

    Method for forming a resist protect layer
    43.
    发明申请
    Method for forming a resist protect layer 有权
    形成抗蚀剂保护层的方法

    公开(公告)号：US20060014396A1

    公开(公告)日：2006-01-19

    申请号：US10892014

    申请日：2004-07-14

    申请人： Chien-Hao Chen ,  Ju-Wang Hsu ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

    发明人： Chien-Hao Chen ,  Ju-Wang Hsu ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

    IPC分类号： H01L21/302 ,  H01L21/31

    CPC分类号： H01L21/31111 ,  H01L21/823481 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78

    摘要： A method for forming a resist protect layer on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. An original nitride layer having a substantial etch selectivity to the isolation structure is formed over the semiconductor substrate. A photoresist mask is formed for partially covering the original nitride layer. A wet etching is performed to remove the original nitride layer uncovered by the photoresist mask in such a way without causing substantial damage to the isolation structure. As such, the original nitride layer covered by the photoresist mask constitutes the resist protect layer.

    摘要翻译： 在半导体衬底上形成抗蚀剂保护层的方法包括以下步骤。 在半导体衬底上形成隔离结构。 在半导体衬底上形成对隔离结构具有实质蚀刻选择性的原始氮化物层。 形成光致抗蚀剂掩模以部分覆盖原始氮化物层。 执行湿蚀刻以以这样的方式去除由光致抗蚀剂掩模未覆盖的原始氮化物层，而不会对隔离结构造成实质损坏。 因此，由光致抗蚀剂掩模覆盖的原始氮化物层构成抗蚀剂保护层。

    Alternative interconnect structure for semiconductor devices
    44.
    发明申请
    Alternative interconnect structure for semiconductor devices 有权
    半导体器件的替代互连结构

    公开(公告)号：US20050285268A1

    公开(公告)日：2005-12-29

    申请号：US10877103

    申请日：2004-06-25

    申请人： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Chun Huang

    发明人： Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Chun Huang

    IPC分类号： H01L21/311 ,  H01L21/336 ,  H01L21/768 ,  H01L23/52

    CPC分类号： H01L21/76802 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76895

    摘要： A semiconductor interconnect structure includes an organic and/or photosensitive etch buffer layer disposed over a contact surface. The structure further provides an interlevel dielectric formed over the etch buffer layer. A method for forming an interconnect structure includes etching to form an opening in the interlevel dielectric, the etching operation being terminated at or above the etch buffer layer. The etch buffer layer is removed to expose the contact surface using a removal process that may include wet etching, ashing or DUV exposure followed by developing or other techniques that do not result in damage to contact surface. The contact surface may be a conductive material such as silicide, salicide or a metal alloy.

    摘要翻译： 半导体互连结构包括设置在接触表面上的有机和/或感光蚀刻缓冲层。 该结构还提供了形成在蚀刻缓冲层上的层间电介质。 用于形成互连结构的方法包括蚀刻以在层间电介质中形成开口，蚀刻操作在蚀刻缓冲层上或其上终止。 去除蚀刻缓冲层以暴露接触表面，使用可以包括湿法蚀刻，灰化或DUV曝光，随后显影的其它技术或不会导致对接触表面损坏的去除工艺。 接触表面可以是导电材料，例如硅化物，硅化物或金属合金。

    Integrated approach for controlling top dielectric loss during spacer etching
    46.
    发明授权
    Integrated approach for controlling top dielectric loss during spacer etching 有权
    在间隔蚀刻期间控制顶部介电损耗的集成方法

    公开(公告)号：US06498067B1

    公开(公告)日：2002-12-24

    申请号：US10139021

    申请日：2002-05-02

    申请人： Baw-Ching Perng ,  Ming-Huang Tsai ,  Ju-Wang Hsu ,  Hun-Jan Tao

    发明人： Baw-Ching Perng ,  Ming-Huang Tsai ,  Ju-Wang Hsu ,  Hun-Jan Tao

    IPC分类号： H01L21336

    CPC分类号： H01L29/665 ,  H01L29/6656

    摘要： A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, has been developed. The process features formation of additional insulator spacer shapes on top portions of sides of a gate structure in which an initial insulator spacer had been removed during an over etch cycle used for definition of the initial insulator spacer. The re-establishment of insulator spacer shapes provides a composite insulator spacer offering reduced risk of gate to substrate leakage or shorts, that can occur during a subsequent salicide procedure from the presence of metal silicide stringers or ribbons formed on, and residing on the composite insulator spacer.

    摘要翻译： 已经开发了在MOSFET栅极结构的侧面上形成复合绝缘体间隔物的工艺。 该工艺特征是在栅极结构的侧面的顶部部分上形成额外的绝缘体间隔物形状，其中在用于限定初始绝缘体间隔物的过蚀刻循环期间已经去除了初始绝缘体间隔物。 重新建立绝缘体间隔物形状提供了一种复合绝缘体间隔物，其降低了栅极与衬底泄漏或短路的风险，这可能在随后的自对准硅化物过程中发生，从存在金属硅化物桁条或形成在复合绝缘体上的带状物 间隔