公开(公告)号：US08017466B2

公开(公告)日：2011-09-13

申请号：US12591162

申请日：2009-11-10

申请人： Kazuaki Nakajima ,  Kyoichi Suguro

发明人： Kazuaki Nakajima ,  Kyoichi Suguro

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/976

摘要： In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the gate electrode of the P-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the concentration of carbon contained in the former tungsten film is less than the concentration of carbon contained in the latter tungsten film.

摘要翻译： 在形成N型MOS晶体管和P型MOS晶体管的半导体衬底中，N型MOS晶体管的栅电极包括与栅极绝缘膜接触的钨膜和栅电极 的P型MOS晶体管包括与栅极绝缘膜接触的钨膜，前者钨膜中所含的碳的浓度小于后者钨膜中所含的碳的浓度。

公开(公告)号：US07968956B2

公开(公告)日：2011-06-28

申请号：US12388965

申请日：2009-02-19

申请人： Kosuke Tatsumura ,  Masakazu Goto ,  Reika Ichihara ,  Masato Koyama ,  Shigeru Kawanaka ,  Kazuaki Nakajima

发明人： Kosuke Tatsumura ,  Masakazu Goto ,  Reika Ichihara ,  Masato Koyama ,  Shigeru Kawanaka ,  Kazuaki Nakajima

IPC分类号： H01L29/78 ,  H01L21/70

CPC分类号： H01L21/823828 ,  H01L21/823842 ,  H01L29/785

摘要： A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.

摘要翻译： 半导体器件包括半导体衬底，形成在衬底上的p沟道MIS晶体管，形成在衬底上的第一栅极电介质的p沟道晶体管和形成在第一电介质上的第一栅极电极层，以及n沟道 形成在衬底上的MIS晶体管，所述n沟道晶体管具有形成在衬底上的第二栅极电介质和形成在第二电介质上的第二栅极电极层。 与第一栅极电介质接触的第一栅极电极层的底层和与第二栅极电介质接触的第二栅电极层的底层具有相同的取向和相同的组成，包括Ta和C，以及摩尔比 的Ta与总计C和Ta（Ta /（Ta + C））大于0.5。

公开(公告)号：US20100291765A1

公开(公告)日：2010-11-18

申请号：US12718449

申请日：2010-03-05

申请人： Kazuaki Nakajima

发明人： Kazuaki Nakajima

IPC分类号： H01L21/28

CPC分类号： H01L29/78 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/4958 ,  H01L29/517

摘要： An aspect of the present disclosure, there is provided a method for fabricating a semiconductor device, including, forming a gate insulating film on a semiconductor substrate, forming a metal film on the gate insulating film, depositing a metal-silicon compound film on the metal film without exposing the semiconductor substrate into atmosphere after forming the metal film, forming a silicon film on the metal-silicon compound film, and etching the metal film, the metal-silicon compound film, and the silicon film.

摘要翻译： 本发明的一个方面提供一种制造半导体器件的方法，包括在半导体衬底上形成栅极绝缘膜，在栅极绝缘膜上形成金属膜，在金属上沉积金属 - 硅化合物膜 在形成金属膜之后不将半导体衬底暴露于大气中，在金属 - 硅化合物膜上形成硅膜，并蚀刻金属膜，金属 - 硅化合物膜和硅膜。

公开(公告)号：US20100288995A1

公开(公告)日：2010-11-18

申请号：US12728028

申请日：2010-03-19

申请人： Yoshio Ozawa ,  Katsuyuki Sekine ,  Kazuaki Nakajima

发明人： Yoshio Ozawa ,  Katsuyuki Sekine ,  Kazuaki Nakajima

IPC分类号： H01L45/00 ,  H01L21/20

CPC分类号： H01L45/1273 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1625 ,  H01L45/1641

摘要： A semiconductor memory device includes: a lower electrode including a plurality of projections formed on a top surface thereof; an oxide film covering the top surface and made of an oxide of a same metal as a metal contained in the lower electrode; and a resistance variable film provided on the oxide film and being in contact with the oxide film, the projections being buried in the oxide film, and a lower layer portion of the resistance variable film having an oxygen concentration lower than an oxygen concentration of a portion other than the lower layer portion of the resistance variable film.

摘要翻译： 半导体存储器件包括：下电极，其包括形成在其顶表面上的多个突起; 覆盖上表面并由与下部电极中所含的金属相同的金属的氧化物构成的氧化膜; 以及设置在氧化膜上并与氧化膜接触的电阻变化膜，所述突起被埋在氧化物膜中，并且电阻变化膜的下层部分的氧浓度低于部分的氧浓度 除了电阻可变膜的下层部分之外。

公开(公告)号：US07820476B2

公开(公告)日：2010-10-26

申请号：US12248143

申请日：2008-10-09

申请人： Kazuaki Nakajima

发明人： Kazuaki Nakajima

IPC分类号： H01L29/78

CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L29/517

摘要： A method for manufacturing a semiconductor device includes: forming a first region and a second region at a main surface of a semiconductor substrate; forming a gate insulating film containing Hf or Zr and oxygen on the first region and the second region; forming a first metallic film on the gate insulating film; forming a second metallic film on the first metallic film; removing a portion of the second metallic film; forming a third metallic film on the second metallic film and a portion of the first metallic film exposed by removing the portion of the second metallic film; and thermally treating so that constituent elements of the second metallic film is diffused into the gate insulating film via the first metallic film.

摘要翻译： 一种制造半导体器件的方法包括：在半导体衬底的主表面处形成第一区域和第二区域; 在所述第一区域和所述第二区域上形成含有Hf或Zr和氧的栅极绝缘膜; 在栅极绝缘膜上形成第一金属膜; 在所述第一金属膜上形成第二金属膜; 去除所述第二金属膜的一部分; 在第二金属膜上形成第三金属膜，通过去除第二金属膜的一部分暴露第一金属膜的一部分; 并进行热处理，使得第二金属膜的构成元件经由第一金属膜扩散到栅极绝缘膜。

公开(公告)号：US20100090292A1

公开(公告)日：2010-04-15

申请号：US12654103

申请日：2009-12-10

申请人： Kazuaki Nakajima

发明人： Kazuaki Nakajima

IPC分类号： H01L29/78

CPC分类号： H01L21/823842

摘要： A method of manufacturing a semiconductor device, comprises: forming a high dielectric gate insulating film in an nMIS formation region and a pMIS formation region of a semiconductor substrate; forming a first metal film on the high dielectric gate insulating film, the first metal film; removing the first metal film in the nMIS formation region; forming a second metal film on the high dielectric gate insulating film of the nMIS formation region and on the first metal film of the pMIS formation region; and processing the first metal film and the second metal film. The high dielectric gate insulating film has a dielectric constant higher than a dielectric constant of silicon oxide. The first metal film does not contain silicon and germanium. The second metal film contains at least one of silicon and germanium.

公开(公告)号：US20100062596A1

公开(公告)日：2010-03-11

申请号：US12591162

申请日：2009-11-10

申请人： Kazuaki Nakajima ,  Kyoichi Suguro

发明人： Kazuaki Nakajima ,  Kyoichi Suguro

IPC分类号： H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/976

摘要： In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the gate electrode of the P-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the concentration of carbon contained in the former tungsten film is less than the concentration of carbon contained in the latter tungsten film.

摘要翻译： 在形成N型MOS晶体管和P型MOS晶体管的半导体衬底中，N型MOS晶体管的栅电极包括与栅极绝缘膜接触的钨膜和栅电极 的P型MOS晶体管包括与栅极绝缘膜接触的钨膜，前者钨膜中所含的碳的浓度小于后者钨膜中所含的碳的浓度。

公开(公告)号：US07667274B2

公开(公告)日：2010-02-23

申请号：US12071887

申请日：2008-02-27

申请人： Kazuaki Nakajima ,  Kyoichi Suguro

发明人： Kazuaki Nakajima ,  Kyoichi Suguro

IPC分类号： H01L29/45 ,  H01L29/78

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/76855 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092

摘要： A semiconductor device is disclosed, which comprises a silicon substrate, a complementary MISFET circuit, an insulation film formed on the silicon substrate, a first contact hole formed in the insulation film, a first metal silicide layer formed on the bottom of the first contact hole, the first metal silicide layer being provided by a reaction of the n-channel impurity diffused region of the n-channel MISFET with a first metal, a second contact hole formed in the insulation film, a second metal silicide layer formed on the bottom of the second contact hole, the second metal silicide layer being provided by a reaction of the p-channel impurity diffused region of the p-channel MISFET with a second metal, and a work function of the second metal silicide layer being higher than that of the first metal silicide layer.

摘要翻译： 公开了一种半导体器件，其包括硅衬底，互补MISFET电路，形成在硅衬底上的绝缘膜，形成在绝缘膜中的第一接触孔，形成在第一接触孔的底部上的第一金属硅化物层 通过n沟道MISFET的n沟道杂质扩散区域与第一金属的反应提供第一金属硅化物层，形成在绝缘膜中的第二接触孔，形成在第二金属硅化物层的底部的第二金属硅化物层 所述第二接触孔，所述第二金属硅化物层由所述p沟道MISFET的p沟道杂质扩散区域与第二金属的反应提供，并且所述第二金属硅化物层的功函数高于所述第二金属硅化物层的功函数 第一金属硅化物层。

公开(公告)号：US20080149932A1

公开(公告)日：2008-06-26

申请号：US11946606

申请日：2007-11-28

申请人： Katsuaki Natori ,  Katsuyuki Sekine ,  Daisuke Nishida ,  Ryota Fujitsuka ,  Masayuki Tanaka ,  Kazuaki Nakajima ,  Yoshio Ozawa ,  Akihito Yamamoto

发明人： Katsuaki Natori ,  Katsuyuki Sekine ,  Daisuke Nishida ,  Ryota Fujitsuka ,  Masayuki Tanaka ,  Kazuaki Nakajima ,  Yoshio Ozawa ,  Akihito Yamamoto

IPC分类号： H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/513 ,  H01L29/7881

摘要： A semiconductor device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate and including a plurality of memory cells arranged on the semiconductor substrate, each of the plurality of the memory cells including a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film provided on the charge storage layer, and a control electrode containing metal or metal silicide provided on the charge storage layer via the second insulating film, wherein a corner of a lower part of the control electrode includes semiconductor and fails to contain the metal or the metal silicide in a channel width direction view of the memory cell.

摘要翻译： 半导体器件包括半导体衬底和设置在半导体衬底上并且包括布置在半导体衬底上的多个存储单元的存储单元阵列，多个存储单元中的每一个包括设置在半导体衬底上的第一绝缘膜， 设置在所述第一绝缘膜上的电荷存储层，设置在所述电荷存储层上的第二绝缘膜，以及经由所述第二绝缘膜设置在所述电荷存储层上的含有金属或金属硅化物的控制电极， 的控制电极包括半导体，并且在存储单元的沟道宽度方向视图中不能容纳金属或金属硅化物。

公开(公告)号：US07354819B2

公开(公告)日：2008-04-08

申请号：US10701435

申请日：2003-11-06

申请人： Kazuaki Nakajima ,  Kyoichi Suguro

发明人： Kazuaki Nakajima ,  Kyoichi Suguro

IPC分类号： H01L21/8238

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/76855 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092

摘要： A semiconductor device is disclosed, which comprises a silicon substrate, a complementary MISFET circuit, an insulation film formed on the silicon substrate, a first contact hole formed in the insulation film, a first metal silicide layer formed on the bottom of the first contact hole, the first metal silicide layer being provided by a reaction of the n-channel impurity diffused region of the n-channel MISFET with a first metal, a second contact hole formed in the insulation film, a second metal silicide layer formed on the bottom of the second contact hole, the second metal silicide layer being provided by a reaction of the p-channel impurity diffused region of the p-channel MISFET with a second metal, and a work function of the second metal silicide layer being higher than that of the first metal silicide layer.

摘要翻译： 公开了一种半导体器件，其包括硅衬底，互补MISFET电路，形成在硅衬底上的绝缘膜，形成在绝缘膜中的第一接触孔，形成在第一接触孔的底部上的第一金属硅化物层 通过n沟道MISFET的n沟道杂质扩散区域与第一金属的反应提供第一金属硅化物层，形成在绝缘膜中的第二接触孔，形成在第二金属硅化物层的底部的第二金属硅化物层 所述第二接触孔，所述第二金属硅化物层由所述p沟道MISFET的p沟道杂质扩散区域与第二金属的反应提供，并且所述第二金属硅化物层的功函数高于所述第二金属硅化物层的功函数 第一金属硅化物层。