公开(公告)号：US20070022250A1

公开(公告)日：2007-01-25

申请号：US11184343

申请日：2005-07-19

申请人： James Fields ,  Guy Guthrie ,  William Starke ,  Phillip Williams

发明人： James Fields ,  Guy Guthrie ,  William Starke ,  Phillip Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0893 ,  G06F12/126 ,  G06F2212/1032

摘要： A system and method of responding to a cache read error with a temporary cache directory column delete. A read command is received at a cache controller. In response to determining that data requested by said read command is stored in a specific data location in the cache, a read of the data is initiated. In response to determining the read of said data results in an error, a column delete indicator for an associativity class including a specific data location to temporarily prevent allocation within the associativity class of storage locations is set. A specific line delete command that marks the specific data location as deleted is issued. In response to the issuing of the specific line delete command, the column delete indicator for the associativity class, such that storage locations within the associativity class other than the specific data location can again be allocated to hold new data is set.

摘要翻译： 使用临时高速缓存目录列删除来响应缓存读取错误的系统和方法。 在高速缓存控制器处接收读命令。 响应于确定由所述读取命令请求的数据被存储在高速缓存中的特定数据位置中，开始读取数据。 响应于确定所述数据的读取导致错误，设置用于包括特定数据位置的关联性类的列删除指示符，以临时阻止存储位置的关联性类别内的分配。 发出将特定数据位置标记为已删除的特定行删除命令。 响应于发出特定行删除命令，设置关联性类的列删除指示符，使得可以再次分配除特定数据位置之外的关联性类中的存储位置以保存新数据。

公开(公告)号：US20060187818A1

公开(公告)日：2006-08-24

申请号：US11054288

申请日：2005-02-09

申请人： James Fields ,  Michael Floyd ,  Benjiman Goodman ,  Paul Lecocq ,  Praveen Reddy

发明人： James Fields ,  Michael Floyd ,  Benjiman Goodman ,  Paul Lecocq ,  Praveen Reddy

IPC分类号： H04J1/16

CPC分类号： G06F11/0793 ,  G06F11/0724

摘要： A method, apparatus, and computer instructions are provided by the present invention to automatically recover from a failed node concurrent maintenance operation. A control logic is provided to send a first test command to processors of a new node. If the first test command is successful, a second test command is sent to all processors or to the remaining nodes if nodes are removed. If the second command is successful, system operation is resumed with the newly configured topology with either nodes added or removed. If the response is incorrect or a timeout has occurred, the control logic restores values to the current mode register and sends a third test command to check for an error. A fatal system attention is sent to a service processor or system software if an error is encountered. If no error, system operation is resumed with previously configured topology.

摘要翻译： 本发明提供了一种方法，装置和计算机指令，以便从故障节点并发维护操作中自动恢复。 提供控制逻辑以将第一测试命令发送到新节点的处理器。 如果第一个测试命令成功，则将第二个测试命令发送到所有处理器或其他节点，如果节点被删除。 如果第二个命令成功，则使用添加或删除节点的新配置的拓扑恢复系统操作。 如果响应不正确或发生超时，控制逻辑将恢复到当前模式寄存器的值，并发送第三个测试命令来检查错误。 如果遇到错误，致命的系统注意事项将发送到服务处理器或系统软件。 如果没有错误，则使用先前配置的拓扑恢复系统操作。

公开(公告)号：US20060184706A1

公开(公告)日：2006-08-17

申请号：US11055847

申请日：2005-02-11

申请人： James Fields ,  Michael Floyd ,  Paul Lecocq

发明人： James Fields ,  Michael Floyd ,  Paul Lecocq

IPC分类号： G06F13/14

CPC分类号： G06F13/1652 ,  Y10S370/916

摘要： The present invention, a multiprocessor chip pervasive command interface, collects different types of pervasive commands into individual queues for each command type. As permitted by various grouping rules, valid commands are grouped together into one single command and placed on a functional interchip communications bus. This grouping of commands maximizes pervasive command bandwidth while the use of the functional bus minimizes the number of interchip connections.

公开(公告)号：US20060179272A1

公开(公告)日：2006-08-10

申请号：US11055297

申请日：2005-02-10

申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F15/00

CPC分类号： G06F13/385 ,  G06F9/546

摘要： A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but fewer than all of the plurality of processing units. Each of the plurality of processing units includes interconnect logic, coupled to each point-to-point communication link of that processing unit, that broadcasts requests received from one of the multiple others of the plurality of processing units to one or more of the plurality of processing units. The interconnect logic includes a partial response data structure including a plurality of entries each associating a partial response field with a plurality of flags respectively associated with each processing unit containing a snooper from which that processing unit will receive a partial response. The interconnect logic accumulates partial responses of processing units by reference to the partial response field to obtain an accumulated partial response, and when the plurality of flags indicate that all processing units from which partial responses are expected have returned a partial response, outputs the accumulated partial response.

摘要翻译： 数据处理系统包括多个处理单元，每个处理单元各自具有与多个处理单元中的多个其他处理单元中的每一个相对的点对点通信链路，但是比所有多个处理单元少。 多个处理单元中的每一个包括互连逻辑，其耦合到该处理单元的每个点对点通信链路，其将从多个处理单元中的多个其中一个的接收的请求广播到多个处理单元中的一个或多个 处理单位。 互连逻辑包括部分响应数据结构，其包括多个条目，每个条目将部分响应字段与分别与包含窥探者的每个处理单元相关联的多个标志相关联，该处理单元将从该处理单元接收部分响应。 互连逻辑通过参考部分响应字段积累处理单元的部分响应以获得累积的部分响应，并且当多个标志指示预期部分响应的所有处理单元已经返回部分响应时，输出累积的部分响应 响应。

公开(公告)号：US20060179254A1

公开(公告)日：2006-08-10

申请号：US11055405

申请日：2005-02-10

申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F15/16

摘要： A data processing system includes a plurality of communication links and a plurality of processing units including a local master processing unit. The local master processing unit includes interconnect logic that couples the processing unit to one or more of the plurality of communication links and an originating master coupled to the interconnect logic. The originating master originates an operation by issuing a write-type request on at least one of the one or more communication links, receives from a snooper in the data processing system a destination tag identifying a route to the snooper, and, responsive to receipt of the combined response and the destination tag, initiates a data transfer including a data payload and a data tag identifying the route provided within the destination tag.

摘要翻译： 数据处理系统包括多个通信链路和包括本地主处理单元的多个处理单元。 本地主处理单元包括将处理单元耦合到多个通信链路中的一个或多个以及耦合到互连逻辑的始发主机的互连逻辑。 始发主机通过在一个或多个通信链路中的至少一个发出写入请求来发起操作，从数据处理系统中的窥探者接收标识到窥探者的路由的目的地标签，并且响应于接收到 组合响应和目的地标签，发起包括数据有效载荷和标识目的地标签内提供的路由的数据标签的数据传输。

公开(公告)号：US20060179253A1

公开(公告)日：2006-08-10

申请号：US11054841

申请日：2005-02-10

申请人： James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0813 ,  G06F2212/1016 ,  G06F2212/1048

摘要： A data processing system includes a memory system, a plurality of masters that issue requests for access to memory blocks within the memory system, a plurality of snoopers that provide partial responses to requests by the masters, and response logic that generates combined responses for the requests in response to the partial responses provided by the plurality of snoopers. The plurality masters includes a winning master that issues a request for a particular memory block, and the plurality of snoopers includes a protecting snooper that, in response to receipt of the request, provides a partial response and protects a transfer of coherency ownership of the particular memory block to the winning master until expiration of a protection window extension following receipt from the response logic of a combined response for the request.

摘要翻译： 数据处理系统包括存储器系统，发出对存储器系统内的存储器块的访问请求的多个主器件，提供对由主器件发出的请求的部分响应的多个监视器以及产生针对请求的组合响应的响应逻辑 响应于由多个窥探者提供的部分响应。 多个主人包括发出对特定存储块的请求的获胜主，并且多个窥探者包括保护窥探者，其响应于该请求的接收而提供部分响应并保护特定存储块的一致性所有权的转移 记忆块到获胜主机，直到从请求的组合响应的响应逻辑接收到保护窗口扩展之后到期。

公开(公告)号：US20060179230A1

公开(公告)日：2006-08-10

申请号：US11055262

申请日：2005-02-10

申请人： James Fields ,  Guy Guthrie ,  Kirk Livingston ,  William Starke

发明人： James Fields ,  Guy Guthrie ,  Kirk Livingston ,  William Starke

IPC分类号： G06F12/00

CPC分类号： G06F12/0851 ,  G06F12/126

摘要： A cache memory logically partitions a cache array into at least two slices each having a plurality of cache lines, with a given cache line spread across two or more cache ways of contiguous bytes and a given cache way shared between the two cache slices, and if one a cache way is defective that is part of a first cache line in the first cache slice and part of a second cache line in the second cache slice, it is disabled while continuing to use at least one other cache way which is also part of the first cache line and part of the second cache line. In the illustrative embodiment the cache array is set associative and at least two different cache ways for a given cache line contain different congruence classes for that cache line. The defective cache way can be disabled by preventing an eviction mechanism from allocating any congruence class in the defective way. For example, half of the cache line can be disabled (i.e., half of the congruence classes). The cache array may be arranged with rows and columns of cache sectors (rows corresponding to the cache ways) wherein a given cache line is further spread across sectors in different rows and columns, with at least one portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency. The cache array can also output different sectors of the given cache line in successive clock cycles based on the latency of a given sector.

摘要翻译： 高速缓存存储器将高速缓存阵列逻辑地分区成至少两个切片，每个切片具有多个高速缓存行，其中给定的高速缓存行分布在连续字节的两个或多个高速缓存路径上以及在两个高速缓存片之间共享的给定高速缓存路径，如果 一个缓存方式是缺陷，其是第一高速缓存片中的第一高速缓存行和第二高速缓存片中的第二高速缓存行的一部分的一部分，其被禁用，同时继续使用至少一种其他高速缓存方式，其也是 第一个缓存行和第二个缓存行的一部分。 在说明性实施例中，高速缓存阵列被设置为关联性，并且给定高速缓存行的至少两个不同的高速缓存路径包含该高速缓存行的不同的一致类。 可以通过防止驱逐机制以有缺陷的方式分配任何一致类来禁用缺陷缓存方式。 例如，可以禁用一半的高速缓存行（即，一致等级的一半）。 高速缓存阵列可以被布置成具有行和列的高速缓存扇区（对应于高速缓存路线的行），其中给定高速缓存行进一步分布在不同行和列中的扇区之间，其中给定高速缓存行的至少一部分位于 具有第一延迟的第一列和给定高速缓存行的另一部分位于具有大于第一等待时间的第二等待时间的第二列中。 缓存阵列还可以基于给定扇区的等待时间在连续的时钟周期中输出给定高速缓存行的不同扇区。

公开(公告)号：US20060179229A1

公开(公告)日：2006-08-10

申请号：US11054924

申请日：2005-02-10

申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke

发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke

IPC分类号： G06F12/00

CPC分类号： G06F12/0851 ,  G06F12/0811

摘要： A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first cache directory to access the first cache array slice while using a second cache directory to access the second cache array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In the illustrative embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. An address tag associated with a load request is transmitted from the processor core with a designated bit that associates the address tag with only one of the cache array slices whose corresponding directory determines whether the address tag matches a currently valid cache entry. The cache array may be arranged with rows and columns of cache sectors wherein a given cache line is spread across sectors in different rows and columns, with at least one portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency. The cache array outputs different sectors of the given cache line in successive clock cycles based on the latency of a given sector.

公开(公告)号：US20060101226A1

公开(公告)日：2006-05-11

申请号：US10982354

申请日：2004-11-05

申请人： Michael Benhase ,  Robert Cargnoni ,  James Fields ,  Michael Mayfield ,  Bruce Mealey

发明人： Michael Benhase ,  Robert Cargnoni ,  James Fields ,  Michael Mayfield ,  Bruce Mealey

IPC分类号： G06F12/10

CPC分类号： G06F12/1081 ,  G06F2212/206

摘要： Provided are a method, system, and program for transferring data directed to virtual memory addresses to a device memory. Indicator bits are set for ranges of device memory addresses in a device accessible over an Input/Output (I/O) bus indicating whether gathering is enabled for the device memory address ranges. Transfer operations are processed to transfer data to contiguous device memory addresses in the device. A determination is made as to whether the indicator bits for the contiguous device memory addresses indicate that gathering is enabled. A single bus I/O transaction is generated to transfer data for the contiguous device memory addresses over the I/O bus in response to determining that the indicator bits for the contiguous device memory addresses indicate that gathering is enabled.

摘要翻译： 提供了用于将指向虚拟存储器地址的数据传送到设备存储器的方法，系统和程序。 指示位设置在可通过输入/输出（I / O）总线访问的设备中的设备存储器地址的范围，指示是否对设备存储器地址范围进行采集。 处理传输操作将数据传输到设备中的连续设备存储器地址。 确定连续设备存储器地址的指示符位是否指示该采集被启用。 响应于确定连续设备存储器地址的指示符位表示启用了集合，生成单总线I / O事务以通过I / O总线传送连续设备存储器地址的数据。