公开(公告)号：US20060187818A1

公开(公告)日：2006-08-24

申请号：US11054288

申请日：2005-02-09

申请人： James Fields ,  Michael Floyd ,  Benjiman Goodman ,  Paul Lecocq ,  Praveen Reddy

发明人： James Fields ,  Michael Floyd ,  Benjiman Goodman ,  Paul Lecocq ,  Praveen Reddy

IPC分类号： H04J1/16

CPC分类号： G06F11/0793 ,  G06F11/0724

摘要： A method, apparatus, and computer instructions are provided by the present invention to automatically recover from a failed node concurrent maintenance operation. A control logic is provided to send a first test command to processors of a new node. If the first test command is successful, a second test command is sent to all processors or to the remaining nodes if nodes are removed. If the second command is successful, system operation is resumed with the newly configured topology with either nodes added or removed. If the response is incorrect or a timeout has occurred, the control logic restores values to the current mode register and sends a third test command to check for an error. A fatal system attention is sent to a service processor or system software if an error is encountered. If no error, system operation is resumed with previously configured topology.

摘要翻译： 本发明提供了一种方法，装置和计算机指令，以便从故障节点并发维护操作中自动恢复。 提供控制逻辑以将第一测试命令发送到新节点的处理器。 如果第一个测试命令成功，则将第二个测试命令发送到所有处理器或其他节点，如果节点被删除。 如果第二个命令成功，则使用添加或删除节点的新配置的拓扑恢复系统操作。 如果响应不正确或发生超时，控制逻辑将恢复到当前模式寄存器的值，并发送第三个测试命令来检查错误。 如果遇到错误，致命的系统注意事项将发送到服务处理器或系统软件。 如果没有错误，则使用先前配置的拓扑恢复系统操作。

公开(公告)号：US20060184706A1

公开(公告)日：2006-08-17

申请号：US11055847

申请日：2005-02-11

申请人： James Fields ,  Michael Floyd ,  Paul Lecocq

发明人： James Fields ,  Michael Floyd ,  Paul Lecocq

IPC分类号： G06F13/14

CPC分类号： G06F13/1652 ,  Y10S370/916

摘要： The present invention, a multiprocessor chip pervasive command interface, collects different types of pervasive commands into individual queues for each command type. As permitted by various grouping rules, valid commands are grouped together into one single command and placed on a functional interchip communications bus. This grouping of commands maximizes pervasive command bandwidth while the use of the functional bus minimizes the number of interchip connections.

公开(公告)号：US20060179251A1

公开(公告)日：2006-08-10

申请号：US11055160

申请日：2005-02-10

申请人： James Fields ,  Michael Floyd ,  Paul Lecocq ,  Larry Leitner ,  Kevin Reick

发明人： James Fields ,  Michael Floyd ,  Paul Lecocq ,  Larry Leitner ,  Kevin Reick

IPC分类号： G06F13/28

CPC分类号： G06F9/3885 ,  G06F9/30003 ,  G06F9/30101 ,  G06F9/30181 ,  G06F12/0888

摘要： In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.

摘要翻译： 在多处理器环境中，通过对寄存器执行高速缓存禁止读或写操作，使用扫描通信来快速访问发起命令的芯片内外的寄存器。 因此可以避免存储器位置的繁琐的锁定。 一开始就设置忙锁实际上消除了冲突的机会，并且设置状态位以通知请求的核心处理器完成命令并且没有错误，如果是这样的话。

公开(公告)号：US20060179184A1

公开(公告)日：2006-08-10

申请号：US11055675

申请日：2005-02-10

申请人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

发明人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

IPC分类号： G06F3/06 ,  G06F3/02 ,  G06F3/00

CPC分类号： G06F15/161

摘要： In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.

摘要翻译： 带内固件执行指令，使指令在一致性结构上发送。 Fabric Snoop逻辑监视针对通过FSI链接附加的支持芯片之一的资源的命令包的一致性结构。 转换逻辑将信息从Fabric数据包转换为FSI协议。 FSI命令通过FSI传输链路发送到预期支持芯片的FSI从站。 FSI接收链路从预期的支持芯片的FSI从站接收响应数据。 转换逻辑将从通过FSI接收链路接收的支持芯片的信息转换为结构协议。 响应分组生成逻辑生成结构响应分组并将其返回到一致性结构上。 支持处理器和支持芯片之间的相同FSI链路允许通过带外固件直接访问支持芯片上的相同资源。

公开(公告)号：US20060176897A1

公开(公告)日：2006-08-10

申请号：US11055404

申请日：2005-02-10

申请人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

发明人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

IPC分类号： H04L12/66

CPC分类号： G06F15/7842

摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

摘要翻译： 提供了一种用于存储器映射资源的支持接口的方法和装置。 支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。 内存映射支持接口更新内存，内存映射寄存器或内存映射资源。 该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。 Fabric命令转换为FSI协议，并转发到附加的支持芯片以访问内存映射资源，并将来自支持芯片的响应转换回Fabric响应数据包。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。 织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。 系统还报告遇到的任何错误。

公开(公告)号：US20060178764A1

公开(公告)日：2006-08-10

申请号：US11054261

申请日：2005-02-09

申请人： Andreas Bieswanger ,  Lee Eisen ,  James Fields ,  Michael Floyd ,  Bradley McCredie ,  Naresh Nayar

发明人： Andreas Bieswanger ,  Lee Eisen ,  James Fields ,  Michael Floyd ,  Bradley McCredie ,  Naresh Nayar

IPC分类号： G05B11/01 ,  G05B19/42

CPC分类号： G06F1/206

摘要： A method, apparatus and computer instructions are provided to autonomically monitor and adjust system characteristics based on a customer optimization goal specified in a policy or profile. An autonomic management component is implemented in firmware comprising a set of control algorithms. Response to reading system characteristics from a plurality of sensors, the autononmic management component selects at least one control algorithm from the set and the control algorithm adjusts the parameters of the system characteristic to optimize performance according to the optimization goal specified by the customer.

摘要翻译： 提供了一种方法，装置和计算机指令，用于基于在策略或简档中指定的客户优化目标自主地监视和调整系统特征。 在包括一组控制算法的固件中实现自主管理组件。 响应于多个传感器的读取系统特性，自动管理部件从集合中选择至少一个控制算法，并且控制算法根据客户指定的优化目标调整系统特性的参数以优化性能。

公开(公告)号：US20070088926A1

公开(公告)日：2007-04-19

申请号：US11250022

申请日：2005-10-13

申请人： James Fields ,  Guy Guthrie ,  John Hollaway ,  Derek Williams

发明人： James Fields ,  Guy Guthrie ,  John Hollaway ,  Derek Williams

IPC分类号： G06F12/14

CPC分类号： G06F12/0831 ,  G06F12/0815 ,  G06F12/0824

摘要： A data processing system includes a plurality of requestors and a memory controller for a system memory. In response to receiving from the requestor a read-type request targeting a memory block in the system memory, the memory controller protects the memory block from modification, and in response to an indication that the memory controller is responsible for servicing the read-type request, the memory controller transmits the memory block to the requestor. Prior to receipt of the memory block by the requestor, the memory controller ends protection of the memory block from modification, and the requestor begins protection of the memory block from modification. In response to receipt of the memory block, the requestor ends its protection of the memory block from modification.

摘要翻译： 数据处理系统包括多个请求者和用于系统存储器的存储器控​​制器。 响应于从请求者接收到针对系统存储器中的存储器块的读取型请求，存储器控制器保护存储器块免受修改，并且响应于存储器控制器负责维护读取类型请求的指示 存储器控制器将该存储器块发送给请求者。 在请求者接收到存储器块之前，存储器控制器结束对存储器块的保护而不被修改，并且请求者开始保护存储器块免受修改。 响应于存储器块的接收，请求者结束其对存储器块的保护以免修改。

公开(公告)号：US20070073919A1

公开(公告)日：2007-03-29

申请号：US11226967

申请日：2005-09-15

申请人： George Daly ,  James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

发明人： George Daly ,  James Fields ,  Guy Guthrie ,  William Starke ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0811

摘要： A data processing system includes at least a first processing node having an input/output (I/O) controller and a second processing including a memory controller for a memory. The memory controller receives, in order, pipelined first and second DMA write operations from the I/O controller, where the first and second DMA write operations target first and second addresses, respectively. In response to the second DMA write operation, the memory controller establishes a state of a domain indicator associated with the second address to indicate an operation scope including the first processing node. In response to the memory controller receiving a data access request specifying the second address and having a scope excluding the first processing node, the memory controller forces the data access request to be reissued with a scope including the first processing node based upon the state of the domain indicator associated with the second address.

摘要翻译： 数据处理系统至少包括具有输入/输出（I / O）控制器的第一处理节点和包括用于存储器的存储器控​​制器的第二处理。 存储器控制器按顺序从I / O控制器接收流水线的第一和第二DMA写入操作，其中第一和第二DMA写操作分别针对第一和第二地址。 响应于第二DMA写入操作，存储器控制器建立与第二地址相关联的域指示符的状态，以指示包括第一处理节点的操作范围。 响应于所述存储器控制器接收到指定所述第二地址并且具有排除所述第一处理节点的范围的数据访问请求，所述存储器控制器基于所述第一处理节点的状态强迫所述数据访问请求被重新发布，所述范围包括所述第一处理节点 与第二个地址关联的域指示符。

公开(公告)号：US20060271741A1

公开(公告)日：2006-11-30

申请号：US11136642

申请日：2005-05-24

申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0813

摘要： In response to execution of program code, a control register within scrubbing logic in a local coherency domain is initialized with at least a target address of a target memory block. In response to the initialization, the scrubbing logic issues to at least one cache hierarchy in a remote coherency domain a domain indication scrubbing request targeting a target memory block that may be cached by the at least one cache hierarchy. In response to receipt of a coherency response indicating that the target memory block is not cached in the remote coherency domain, a domain indication in the local coherency domain is updated to indicate that the target memory block is cached, if at all, only within the local coherency domain.

摘要翻译： 响应于程序代码的执行，用至少目标存储器块的目标地址初始化局部一致性域内的擦除逻辑中的控制寄存器。 响应于初始化，擦除逻辑向远程一致性域中的至少一个高速缓存层级发出针对可由所述至少一个高速缓存层级缓存的目标存储器块的域指示擦除请求。 响应于接收到指示目标存储器块未被缓存在远程一致性域中的一致性响应，本地一致性域中的域指示被更新以指示目标存储器块被缓存，如果完全只在 局部一致性域。

公开(公告)号：US20060190636A1

公开(公告)日：2006-08-24

申请号：US11054183

申请日：2005-02-09

申请人： George Daly ,  James Fields

发明人： George Daly ,  James Fields

IPC分类号： G06F13/28

CPC分类号： G06F12/0835 ,  G06F13/28

摘要： A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.

摘要翻译： 公开了一种在直接存储器访问（DMA）写入操作期间使高速缓存线无效的方法和装置。 最初，外围设备发出多高速缓存行DMA请求。 多高速缓存行DMA请求被缓存内存窥探。 然后确定高速缓冲存储器是否包括存储在多高速缓存行DMA请求所针对的系统存储单元中的数据的副本。 响应于确定高速缓冲存储器包括存储在多高速缓存行DMA请求所针对的系统存储器位置中的数据的副本，高速缓冲存储器内的多个高速缓存行连续无效。