公开(公告)号：US20180323269A1

公开(公告)日：2018-11-08

申请号：US15585865

申请日：2017-05-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Kwan-Yong Lim ,  Hui Zhan

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed includes, among other things, forming a gate around an initial fin structure and above a layer of insulating material, and performing a fin trimming process on an exposed portion of the initial fin structure in the source/drain region so as to produce a reduced-size fin portion positioned above a surface of a layer of insulating material in the source/drain region of the device, wherein the the reduced-size fin portion has a second size that is less than the first size. In this example, the method also includes forming a conformal epi semiconductor material on the reduced-size fin portion and forming a conductive source/drain contact structure that is conductively coupled to and wrapped around the conformal epi semiconductor material