公开(公告)号：US10468310B2

公开(公告)日：2019-11-05

申请号：US15334964

申请日：2016-10-26

申请人： GLOBALFOUNDRIES INC.

发明人： Jianwei Peng ,  Xusheng Wu

IPC分类号： H01L21/8238 ,  H01L21/762 ,  H01L27/092

摘要： The present disclosure relates to semiconductor structures and, more particularly, to a spacer integration scheme for both NFET and PFET devices and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for NFET devices having sidewall spacers of a first dimension; and a plurality epitaxial grown fin structures for PFET devices having sidewall spacers of the first dimension.

公开(公告)号：US10431665B2

公开(公告)日：2019-10-01

申请号：US15875055

申请日：2018-01-19

申请人： GLOBALFOUNDRIES Inc.

发明人： Tao Han ,  Zhenyu Hu ,  Jinping Liu ,  Hsien-Ching Lo ,  Jianwei Peng

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/78

摘要： Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.

公开(公告)号：US20190221515A1

公开(公告)日：2019-07-18

申请号：US15872589

申请日：2018-01-16

申请人： GLOBALFOUNDRIES Inc.

发明人： Sipeng Gu ,  Jianwei Peng ,  Xusheng Wu ,  Yi Qi ,  Jeffrey Chee

IPC分类号： H01L23/522 ,  H01L49/02 ,  H01L21/768

摘要： Structures that include a metal-insulator-metal (MIM) capacitor and methods for fabricating a structure that includes a MIM capacitor. The MIM capacitor includes a first electrode, a second electrode, and a third electrode. A conductive via is arranged in a via opening extending in a vertical direction through at least the first electrode. The first electrode has a surface arranged inside the via opening in a plane transverse to the vertical direction, and the conductive via contacts the first electrode over an area of the surface.

公开(公告)号：US10297675B1

公开(公告)日：2019-05-21

申请号：US15795879

申请日：2017-10-27

申请人： GLOBALFOUNDRIES Inc.

发明人： Alina Vinslava ,  Hsien-Ching Lo ,  Yongjun Shi ,  Jianwei Peng ,  Jianghu Yan ,  Yi Qi

IPC分类号： H01L21/84 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08

摘要： Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.

公开(公告)号：US10068810B1

公开(公告)日：2018-09-04

申请号：US15697661

申请日：2017-09-07

申请人： GLOBALFOUNDRIES INC.

发明人： Xusheng Wu ,  Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Sipeng Gu

IPC分类号： H01L21/84 ,  H01L21/762 ,  H01L21/02 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/308

摘要： A method of forming semiconductor fins having different fin heights and which are dielectrically isolated from an underlying semiconductor substrate. The fins may be formed by etching an active epitaxial layer that is disposed over the substrate. An intervening sacrificial epitaxial layer may be used to template growth of the active epitaxial layer, and is then removed and backfilled with an isolation dielectric layer. The isolation dielectric layer may be disposed between bottom surfaces of the fins and the substrate, and may be deposited, for example, following the etching process used to define the fins. Within different regions of the substrate, dielectrically isolated fins of different heights may have substantially co-planar top surfaces.

公开(公告)号：US09490174B2

公开(公告)日：2016-11-08

申请号：US14279480

申请日：2014-05-16

申请人： GLOBALFOUNDRIES Inc.

发明人： Xusheng Wu ,  Jianwei Peng ,  Min-hwa Chi

IPC分类号： H01L21/8234 ,  H01L21/02

CPC分类号： H01L21/823431 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/823437 ,  H01L21/823475

摘要： A method of fabricating a raised fin structure including a raised contact structure is provided. The method may include: providing a base fin structure; providing at least one ancillary fin structure, the at least one ancillary fin structure contacting the base fin structure at a side of the base fin structure; growing a material over the base fin structure to form the raised fin structure; and, growing the material over the at least one ancillary fin structure, wherein the at least one ancillary fin structure contacting the base fin structure increases a volume of material grown over the base fin structure near the contact between the base fin structure and the at least one ancillary fin structure to form the raised contact structure.

摘要翻译： 提供了一种制造包括凸起接触结构的凸起鳍结构的方法。 该方法可以包括：提供底鳍结构; 提供至少一个辅助翅片结构，所述至少一个辅助翅片结构在所述基部翅片结构的一侧与所述底部翅片结构接触; 在基板结构上生长材料以形成凸起的翅片结构; 并且在所述至少一个辅助翅片结构上生长所述材料，其中所述至少一个辅助翅片结构接触所述基底翅片结构增加了在所述基底翅片结构与所述至少 一个辅助翅片结构形成凸起的接触结构。

公开(公告)号：US10453754B1

公开(公告)日：2019-10-22

申请号：US16021660

申请日：2018-06-28

申请人： GLOBALFOUNDRIES Inc.

发明人： Jianwei Peng ,  Haigou Huang ,  Qun Gao ,  Xin Wang

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L21/324 ,  H01L21/02 ,  H01L21/225

摘要： The present disclosure is directed to various methods of diffusing contact extension dopants in a transistor device and the resulting devices. One illustrative method includes forming a first contact opening between two adjacent gate structures formed above a first fin, the first contact opening exposing a first region of the first fin, forming a first contact recess in the first region, forming a first doped liner in the first contact recess, performing an anneal process to diffuse dopants from the first doped liner into the first fin to form a first doped contact extension region in the first fin, and performing a first epitaxial growth process to form a first source/drain region in the first contact recess.

公开(公告)号：US10211317B1

公开(公告)日：2019-02-19

申请号：US15869349

申请日：2018-01-12

申请人： GLOBALFOUNDRIES Inc.

发明人： Yi Qi ,  Xusheng Wu ,  Jianwei Peng ,  Sipeng Gu ,  Hsien-Ching Lo

IPC分类号： H01L29/76 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L29/78 ,  H01L21/3105

摘要： Methods of forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed over a sacrificial layer. A support structure is connected with the semiconductor fin. After forming the support structure, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin. A semiconductor material is epitaxially grown in the cavity to form a source/drain region of the vertical-transport field-effect transistor.

公开(公告)号：US20180114730A1

公开(公告)日：2018-04-26

申请号：US15334964

申请日：2016-10-26

申请人： GLOBALFOUNDRIES INC.

发明人： Jianwei Peng ,  Xusheng Wu

IPC分类号： H01L21/8238 ,  H01L21/762 ,  H01L21/02

摘要： The present disclosure relates to semiconductor structures and, more particularly, to a spacer integration scheme for both NFET and PFET devices and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for NFET devices having sidewall spacers of a first dimension; and a plurality epitaxial grown fin structures for PFET devices having sidewall spacers of the first dimension.

公开(公告)号：US09947769B1

公开(公告)日：2018-04-17

申请号：US15363461

申请日：2016-11-29

申请人： GLOBALFOUNDRIES Inc.

发明人： Tao Han ,  Zhenyu Hu ,  Jinping Liu ,  Hsien-Ching Lo ,  Jianwei Peng

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC分类号： H01L29/6656 ,  H01L21/0214 ,  H01L21/0228 ,  H01L29/66795 ,  H01L29/785

摘要： Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer is located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer is located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.