公开(公告)号：US10192746B1

公开(公告)日：2019-01-29

申请号：US15665183

申请日：2017-07-31

申请人： GLOBALFOUNDRIES, Inc.

发明人： Ashish Kumar Jha ,  Hui Zhan ,  Hong Yu ,  Zhenyu Hu ,  Haiting Wang ,  Edward Reis ,  Charles Vanleuvan

IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/475

摘要： A shallow trench isolation (STI) structure is formed from a conventional STI trench structure formed of first dielectric material extending into the substrate. The conventional STI structure undergoes further processing, including removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride layer is formed above remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses. The nitride layer provides an “inner spacer” between the first insulating material and the second insulating material and also separates the substrate from the second insulating material. An isotropic Fin reveal process is performed and the STI structure assists in equalizing fin heights and increasing active S/D region area/volume.

公开(公告)号：US10784342B1

公开(公告)日：2020-09-22

申请号：US16385197

申请日：2019-04-16

申请人： GLOBALFOUNDRIES Inc.

发明人： Wei Hong ,  Hong Yu ,  Jianwei Peng ,  Hui Zhan

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66

摘要： Structures that include a single diffusion break and methods of forming a single diffusion break. A source/drain region is arranged inside a first cavity in a semiconductor fin, and a dielectric layer is arranged inside a second cavity in the semiconductor fin. A liner, which is composed of a dielectric material, includes a section that is arranged inside the second cavity laterally between the dielectric layer and the source/drain region.

公开(公告)号：US10586860B2

公开(公告)日：2020-03-10

申请号：US15970217

申请日：2018-05-03

申请人： GLOBALFOUNDRIES INC.

发明人： Jiehui Shu ,  Laertis Economikos ,  Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Hui Zhan ,  Tao Han ,  Haiting Wang ,  Jinping Liu ,  Hui Zang

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/3065

摘要： In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

公开(公告)号：US10121868B1

公开(公告)日：2018-11-06

申请号：US15585865

申请日：2017-05-03

申请人： GLOBALFOUNDRIES Inc.

发明人： Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Kwan-Yong Lim ,  Hui Zhan

IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： One illustrative method disclosed includes, among other things, forming a gate around an initial fin structure and above a layer of insulating material, and performing a fin trimming process on an exposed portion of the initial fin structure in the source/drain region so as to produce a reduced-size fin portion positioned above a surface of a layer of insulating material in the source/drain region of the device, wherein the the reduced-size fin portion has a second size that is less than the first size. In this example, the method also includes forming a conformal epi semiconductor material on the reduced-size fin portion and forming a conductive source/drain contact structure that is conductively coupled to and wrapped around the conformal epi semiconductor material.

公开(公告)号：US09887094B1

公开(公告)日：2018-02-06

申请号：US15585800

申请日：2017-05-03

申请人： GLOBALFOUNDRIES Inc.

发明人： Yi Qi ,  Hsien-Ching Lo ,  Jianwei Peng ,  Yanping Shen ,  Hui Zhan

IPC分类号： H01L21/3105 ,  H01L29/66 ,  H01L29/08 ,  H01L21/311

CPC分类号： H01L21/31053 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

摘要： One illustrative method disclosed includes, among other things, forming a fin spacer adjacent a lower portion of a fin that is comprised of a fin spacer material, forming a conformal layer of a second spacer material on the exposed sidewalls and the upper surface of the fin, on the fin spacer and adjacent a gate structure of the FinFET device, wherein the second spacer material is a different material than the fin spacer material, performing an etching process to remove the second conformal layer from above the fin spacer to thereby re-expose the sidewalls of the fin above the fin spacer and the upper surface of the fin while forming a gate spacer comprising the second spacer material adjacent the gate structure, and forming an epi semiconductor material on the exposed sidewalls and upper surface of the fins above the first fin spacer.

公开(公告)号：US09620381B2

公开(公告)日：2017-04-11

申请号：US14050472

申请日：2013-10-10

申请人： GLOBALFOUNDRIES Inc.

发明人： Suraj K. Patil ,  Huy Cao ,  Hui Zhan ,  Huang Liu

IPC分类号： H01L21/311 ,  H01L29/66 ,  H01L21/3115

CPC分类号： H01L21/31105 ,  H01L21/31116 ,  H01L21/31155 ,  H01L29/66795

摘要： Methods of facilitating fabrication of circuit structures are provided which include, for instance: providing a structure with a film layer; modifying an etch property of the film layer by implanting at least one species of element or molecule into the upper portion of the film layer, the etch property of the film layer remaining unmodified beneath the upper portion; and subjecting the structure and film layer with the modified etch property to an etching process, the modified etch property of the film layer facilitating the etching process. Modifying the etch property of the upper portion of the film layer may include making the upper portion of the film layer preferentially susceptible or preferentially resistant to the etching process depending on the circuit fabrication approach being facilitated.

公开(公告)号：US20190341475A1

公开(公告)日：2019-11-07

申请号：US15970217

申请日：2018-05-03

申请人： GLOBALFOUNDRIES INC.

发明人： Jiehui Shu ,  Laertis Economikos ,  Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Hui Zhan ,  Tao Han ,  Haiting Wang ,  Jinping Liu ,  Hui Zang

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238

摘要： In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

公开(公告)号：US20190312117A1

公开(公告)日：2019-10-10

申请号：US15949730

申请日：2018-04-10

申请人： GLOBALFOUNDRIES Inc.

发明人： Yi Qi ,  Hsien-Ching Lo ,  Hong Yu ,  Yanping Shen ,  Wei Hong ,  Xing Zhang ,  Ruilong Xie ,  Haiting Wang ,  Hui Zhan ,  Yong Jun Shi

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/45 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02

摘要： One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure.

公开(公告)号：US20180323269A1

公开(公告)日：2018-11-08

申请号：US15585865

申请日：2017-05-03

申请人： GLOBALFOUNDRIES Inc.

发明人： Yi Qi ,  Jianwei Peng ,  Hsien-Ching Lo ,  Kwan-Yong Lim ,  Hui Zhan

IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： One illustrative method disclosed includes, among other things, forming a gate around an initial fin structure and above a layer of insulating material, and performing a fin trimming process on an exposed portion of the initial fin structure in the source/drain region so as to produce a reduced-size fin portion positioned above a surface of a layer of insulating material in the source/drain region of the device, wherein the the reduced-size fin portion has a second size that is less than the first size. In this example, the method also includes forming a conformal epi semiconductor material on the reduced-size fin portion and forming a conductive source/drain contact structure that is conductively coupled to and wrapped around the conformal epi semiconductor material

公开(公告)号：US09059218B2

公开(公告)日：2015-06-16

申请号：US14030506

申请日：2013-09-18

申请人： GLOBALFOUNDRIES Inc.

发明人： Bharat Krishnan ,  Jinping Liu ,  Zhao Lun ,  Hui Zhan ,  Bongki Lee

IPC分类号： H01L21/22 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225

CPC分类号： H01L29/6681 ,  H01L21/2253 ,  H01L21/2652 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor structure includes a semiconductor substrate, an active region and a dummy gate structure disposed over the active region. A sacrificial conformal layer, including a bottom oxide layer and a top nitride layer are provided over the dummy gate structure and active region to protect the dummy gate during source and drain implantation. The active region is implanted using dopants such as, a n-type dopant or a p-type dopant to create a source region and a drain region in the active region, after which the sacrificial conformal layer is removed.

摘要翻译： 半导体结构包括设置在有源区上的半导体衬底，有源区和伪栅极结构。 在伪栅极结构和有源区域上设置包括底部氧化物层和顶部氮化物层的牺牲保形层，以在源极和漏极注入期间保护虚拟栅极。 使用诸如n型掺杂剂或p型掺杂剂的掺杂剂注入有源区域，以在有源区域中产生源极区域和漏极区域，之后去除牺牲保形层。