公开(公告)号：US20140264631A1

公开(公告)日：2014-09-18

申请号：US13834608

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy C. Wei ,  Jeong Soo Kim ,  Francis M. Tambwe

IPC: H01L21/762 ,  H01L21/3105 ,  H01L27/088

CPC classification number: H01L23/544 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0886 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart fin structures in a semiconductor substrate, wherein the fin structures define a portion of an alignment/overlay mark trench where at least a portion of an alignment/overlay mark will be formed, forming at least one layer of insulating material that overfills the alignment/overlay mark trench and removing excess portions of the layer of insulating material positioned above an upper surface of the plurality of fins to thereby define at least a portion of the alignment/overlay mark positioned within the alignment/overlay mark trench. A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to partially define an alignment/overlay mark trench, an alignment/overlay mark consisting only of at least one insulating material positioned within the alignment/overlay mark trench, and a plurality of FinFET semiconductor devices formed in and above the substrate.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成多个间隔开的翅片结构，其中鳍结构限定对准/覆盖标记沟槽的一部分，其中将形成至少一部分对准/覆盖标记，形成 至少一层绝缘材料，其过度填充对准/覆盖标记沟槽，并且移除位于多个翅片的上表面上方的绝缘材料层的多余部分，从而限定定位/重叠标记的至少一部分 对准/重叠标记沟槽。 本文公开的装置包括形成在半导体衬底中的多个间隔开的翅片结构，以便部分地限定对准/覆盖标记沟槽，对准/覆盖标记仅由位于对准/覆盖标记内的至少一个绝缘材料组成 沟槽，以及形成在衬底中和上方的多个FinFET半导体器件。

公开(公告)号：US08609510B1

公开(公告)日：2013-12-17

申请号：US13623893

申请日：2012-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Srinvasa Banna ,  Andy C. Wei

IPC: H01L21/76

CPC classification number: H01L21/76224 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: Embodiments of the invention provide approaches for replacement metal gate (RMG) diffusion break formation. Specifically, a diffusion break is created after source/drain (S/D) formation, thereby allowing facet free and high quality S/D formation. A dummy gate body is removed selective to a sidewall section of a capping layer and a GOx layer formed over a substrate, and the opening is then extended through the GOx layer and into the substrate by etching the dummy gate body selective to the sidewall section of the capping layer. Retaining the capping layer during the dummy gate body etch enables the diffusion break to be self-aligned to the gate and eliminates device variability due to S/D volume variations. Processing then continues with RMG poly open chemical mechanical planarization (POC) and poly open planarization (POP).

Abstract translation: 本发明的实施例提供了替代金属栅极（RMG）扩散断裂形成的方法。 具体地说，在源极/漏极（S / D）形成之后产生扩散断裂，从而允许无小面积和高质量的S / D形成。 选择性地对封盖层的侧壁部分和形成在基板上的GOx层进行选择性的虚拟栅极体，然后通过蚀刻对该侧壁部分的侧壁部分选择性的虚拟栅极体，将开口延伸穿过GOx层并进入基板 盖层。 在虚拟门体蚀刻期间保持覆盖层使得扩散断裂能够自对准到栅极并消除由于S / D体积变化引起的器件变异性。 然后处理继续使用RMG多开放化学机械平面化（POC）和多孔平面化（POP）。