公开(公告)号：US20150123214A1

公开(公告)日：2015-05-07

申请号：US14595924

申请日：2015-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/10 ,  H01L27/088

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures.

Abstract translation: FinFET器件包括位于半导体衬底中和上方的多个翅片结构，其中每个翅片结构包括半导体衬底的第一部分，位于半导体衬底的第一部分上方的未掺杂的半导体材料层，以及 位于半导体衬底的第一部分和未掺杂的半导体材料之间的半导体材料含掺杂剂层，其中掺杂剂材料适于延迟硼和磷中的一种的扩散。 栅电极至少围绕多个翅片结构中的每一个的半导体材料的未掺杂层定位，其中栅电极的底表面的高度水平位于与底部的高度水平近似等于或低于 所述多个翅片结构中的每一个的未掺杂的半导体材料层。

公开(公告)号：US09275890B2

公开(公告)日：2016-03-01

申请号：US13834608

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Jeong Soo Kim ,  Francis M. Tambwe

IPC: H01L21/76 ,  H01L21/762 ,  H01L23/544 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L23/544 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0886 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart fin structures in a semiconductor substrate, wherein the fin structures define a portion of an alignment/overlay mark trench where at least a portion of an alignment/overlay mark will be formed, forming at least one layer of insulating material that overfills the alignment/overlay mark trench and removing excess portions of the layer of insulating material positioned above an upper surface of the plurality of fins to thereby define at least a portion of the alignment/overlay mark positioned within the alignment/overlay mark trench. A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to partially define an alignment/overlay mark trench, an alignment/overlay mark consisting only of at least one insulating material positioned within the alignment/overlay mark trench, and a plurality of FinFET semiconductor devices formed in and above the substrate.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成多个间隔开的翅片结构，其中鳍结构限定对准/覆盖标记沟槽的一部分，其中将形成至少一部分对准/覆盖标记，形成 至少一层绝缘材料，其过度填充对准/覆盖标记沟槽，并且移除位于多个翅片的上表面上方的绝缘材料层的多余部分，从而限定定位/重叠标记的至少一部分 对准/重叠标记沟槽。 本文公开的装置包括形成在半导体衬底中的多个间隔开的翅片结构，以便部分地限定对准/覆盖标记沟槽，对准/覆盖标记仅由位于对准/覆盖标记内的至少一个绝缘材料组成 沟槽，以及形成在衬底中和上方的多个FinFET半导体器件。

公开(公告)号：US09105507B2

公开(公告)日：2015-08-11

申请号：US14595924

申请日：2015-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/76 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures.

Abstract translation: FinFET器件包括位于半导体衬底中和上方的多个翅片结构，其中每个翅片结构包括半导体衬底的第一部分，位于半导体衬底的第一部分上方的未掺杂的半导体材料层，以及 位于半导体衬底的第一部分和未掺杂的半导体材料之间的半导体材料含掺杂剂层，其中掺杂剂材料适于延迟硼和磷中的一种的扩散。 栅电极至少围绕多个翅片结构中的每一个的半导体材料的未掺杂层定位，其中栅电极的底表面的高度水平位于与底部的高度水平近似等于或低于 所述多个翅片结构中的每一个的未掺杂的半导体材料层。

公开(公告)号：US08969932B2

公开(公告)日：2015-03-03

申请号：US13711779

申请日：2012-12-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.

Abstract translation: 本文公开的一种方法包括：在用于器件的半导体衬底中形成隔离区之前，在衬底中形成掺杂阱区和掺杂的穿通停止区，引入适于延迟硼或磷扩散的掺杂​​材料 进入衬底以在衬底的上表面附近形成含掺杂剂的层，执行外延沉积工艺以在掺杂剂层之上形成未掺杂的半导体材料，形成多个间隔开的沟槽，其至少部分延伸到 衬底，其中所述沟槽限定用于由至少所述未掺杂的半导体材料构成的器件的鳍，在所述沟槽中形成至少一个局部隔离绝缘材料，以及形成至少所述未掺杂的半导体材料周围的栅极结构，其中， 栅极位于与未掺杂的半导体材料的底部大致平齐的位置。

公开(公告)号：US20140159126A1

公开(公告)日：2014-06-12

申请号：US13711779

申请日：2012-12-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: One method disclosed herein includes, prior to forming an isolation region in a semiconducting substrate for the device, forming a doped well region and a doped punch-stop region in the substrate, introducing a dopant material that is adapted to retard diffusion of boron or phosphorous into the substrate to form a dopant-containing layer proximate an upper surface of the substrate, performing an epitaxial deposition process to form an undoped semiconducting material above the dopant-containing layer, forming a plurality of spaced-apart trenches that extend at least partially into the substrate, wherein the trenches define a fin for the device comprised of at least the undoped semiconducting material, forming at least a local isolation insulating material in the trenches, and forming a gate structure around at least the undoped semiconducting material, wherein a bottom of a gate electrode is positioned approximately level with or below a bottom of the undoped semiconducting material.

Abstract translation: 本文公开的一种方法包括：在用于器件的半导体衬底中形成隔离区之前，在衬底中形成掺杂阱区和掺杂的穿通停止区，引入适于延迟硼或磷扩散的掺杂​​材料 进入衬底以在衬底的上表面附近形成含掺杂剂的层，执行外延沉积工艺以在掺杂剂层之上形成未掺杂的半导体材料，形成多个间隔开的沟槽，其至少部分延伸到 衬底，其中所述沟槽限定用于由至少所述未掺杂的半导体材料构成的器件的鳍，在所述沟槽中形成至少一个局部隔离绝缘材料，以及形成至少所述未掺杂的半导体材料周围的栅极结构，其中， 栅极位于与未掺杂的半导体材料的底部大致平齐的位置。

公开(公告)号：US09515026B2

公开(公告)日：2016-12-06

申请号：US15001584

申请日：2016-01-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Jeong Soo Kim ,  Francis M. Tambwe

IPC: H01L23/544 ,  H01L21/762 ,  H01L27/088 ,  H01L21/308 ,  H01L27/02 ,  H01L21/8234

CPC classification number: H01L23/544 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0886 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to define an alignment/overlay mark trench. An alignment/overlay mark includes at least one insulating material positioned within the alignment/overlay mark trench. The alignment/overlay mark is devoid of any of the fin structures.

Abstract translation: 本文公开的装置包括形成在半导体衬底中的多个间隔开的翅片结构，以便限定对准/覆盖标记沟槽。 对准/覆盖标记包括位于对准/覆盖标记沟槽内的至少一个绝缘材料。 对齐/重叠标记没有任何翅片结构。

公开(公告)号：US20160141252A1

公开(公告)日：2016-05-19

申请号：US15001584

申请日：2016-01-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Jeong Soo Kim ,  Francis M. Tambwe

IPC: H01L23/544 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L23/544 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0886 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to define an alignment/overlay mark trench. An alignment/overlay mark includes at least one insulating material positioned within the alignment/overlay mark trench. The alignment/overlay mark is devoid of any of the fin structures.

Abstract translation: 本文公开的装置包括形成在半导体衬底中的多个间隔开的翅片结构，以便限定对准/覆盖标记沟槽。 对准/覆盖标记包括位于对准/覆盖标记沟槽内的至少一个绝缘材料。 对齐/重叠标记没有任何翅片结构。

公开(公告)号：US20140264631A1

公开(公告)日：2014-09-18

申请号：US13834608

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy C. Wei ,  Jeong Soo Kim ,  Francis M. Tambwe

IPC: H01L21/762 ,  H01L21/3105 ,  H01L27/088

CPC classification number: H01L23/544 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0886 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart fin structures in a semiconductor substrate, wherein the fin structures define a portion of an alignment/overlay mark trench where at least a portion of an alignment/overlay mark will be formed, forming at least one layer of insulating material that overfills the alignment/overlay mark trench and removing excess portions of the layer of insulating material positioned above an upper surface of the plurality of fins to thereby define at least a portion of the alignment/overlay mark positioned within the alignment/overlay mark trench. A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to partially define an alignment/overlay mark trench, an alignment/overlay mark consisting only of at least one insulating material positioned within the alignment/overlay mark trench, and a plurality of FinFET semiconductor devices formed in and above the substrate.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成多个间隔开的翅片结构，其中鳍结构限定对准/覆盖标记沟槽的一部分，其中将形成至少一部分对准/覆盖标记，形成 至少一层绝缘材料，其过度填充对准/覆盖标记沟槽，并且移除位于多个翅片的上表面上方的绝缘材料层的多余部分，从而限定定位/重叠标记的至少一部分 对准/重叠标记沟槽。 本文公开的装置包括形成在半导体衬底中的多个间隔开的翅片结构，以便部分地限定对准/覆盖标记沟槽，对准/覆盖标记仅由位于对准/覆盖标记内的至少一个绝缘材料组成 沟槽，以及形成在衬底中和上方的多个FinFET半导体器件。