公开(公告)号：US20140068174A1

公开(公告)日：2014-03-06

申请号：US13598448

申请日：2012-08-29

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F12/00

CPC classification number: G06F9/467 ,  G06F9/3004 ,  G06F9/30087 ,  H04L45/745 ,  H04L47/2441

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a base address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). A selecting circuit within the TM uses the starting bit position and the mask size to select a first portion of the IV. The first portion of the IV and the base address value are summed to generate a memory address. The memory address is used to read a word containing multiple result values and multiple reference values from memory. A second portion of the IV is compared with each reference value using a comparator circuit. A result value associated with the matching reference value is selected using a multiplexing circuit and a select value generated by the comparator circuit. The TM sends the selected result value to the processor.

Abstract translation: 事务存储器（TM）从处理器接收总线上的查找命令。 该命令包括基地址，起始位位置和掩码大小。 响应该命令，TM拉动输入值（IV）。 TM内的选择电路使用起始位位置和掩模尺寸来选择IV的第一部分。 IV的第一部分和基地址值相加以生成存储器地址。 存储器地址用于从存储器读取包含多个结果值和多个参考值的单词。 使用比较器电路将IV的第二部分与每个参考值进行比较。 使用复用电路和由比较器电路产生的选择值来选择与匹配参考值相关联的结果值。 TM将选定的结果值发送到处理器。

公开(公告)号：US20140068109A1

公开(公告)日：2014-03-06

申请号：US13598533

申请日：2012-08-29

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F3/00

CPC classification number: G06F9/467 ,  G06F12/00 ,  G06F13/1615 ,  G06F13/287 ,  G06F13/4022 ,  G06F13/4234 ,  H04L45/745 ,  Y02D10/14 ,  Y02D10/151

Abstract: A transactional memory (TM) receives an Atomic Metering Command (AMC) across a bus from a processor. The command includes a memory address and a meter pair indicator value. In response to the AMC, the TM pulls an input value (IV). The TM uses the memory address to read a word including multiple credit values from a memory unit. Circuitry within the TM selects a pair of credit values, subtracts the IV from each of the pair of credit values thereby generating a pair of decremented credit values, compares the pair of decremented credit values with a threshold value, respectively, thereby generating a pair of indicator values, performs a lookup based upon the pair of indicator values and the meter pair indicator value, and outputs a selector value and a result value that represents a meter color. The selector value determines the credit values written back to the memory unit.

Abstract translation: 事务存储器（TM）从处理器接收总线上的原子计量命令（AMC）。 该命令包括存储器地址和仪表对指示器值。 对于AMC，TM提取输入值（IV）。 TM使用存储器地址从存储器单元读取包括多个信用值的单词。 TM内的电路选择一对信用值，从该对信用值中的每一个中减去IV，从而生成一对递减的信用值，将一对递减的信用值与阈值进行比较，从而产生一对 指示符值，根据指示符值对和仪表对指示符值执行查找，并输出选择器值和表示仪表颜色的结果值。 选择器值确定写入存储单元的信用值。

公开(公告)号：US20140025919A1

公开(公告)日：2014-01-23

申请号：US13552619

申请日：2012-07-18

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F12/10

CPC classification number: G06F13/1615 ,  G06F9/3004 ,  G06F9/34 ,  G06F9/35 ,  G06F9/467 ,  G06F13/1663 ,  G06F13/40

Abstract: A lookup engine of a transactional memory (TM) has multiple hardware lookup structures, each usable to perform a different type of lookup. In response to a lookup command, the lookup engine reads a first block of first information from a memory unit. The first information configures the lookup engine to perform a first type of lookup, thereby identifying a first result value. If the first result value is not a final result value, then the lookup engine uses address information in the first result value to read a second block of second information. The second information configures the lookup engine to perform a second type of lookup, thereby identifying a second result value. This process repeats until a final result value is obtained. The type of lookup performed is determined by the result value of the preceding lookup and/or type information of the block of information for the next lookup.

Abstract translation: 事务存储器（TM）的查找引擎具有多个硬件查找结构，每个硬件查找结构可用于执行不同类型的查找。 响应于查找命令，查找引擎从存储器单元读取第一信息块。 第一信息配置查找引擎执行第一类型的查找，从而识别第一结果值。 如果第一结果值不是最终结果值，则查找引擎使用第一结果值中的地址信息来读取第二信息块。 第二信息配置查找引擎执行第二类型的查找，从而识别第二结果值。 该过程重复，直到获得最终结果值。 执行的查找类型由下一次查找的信息块的前一查找和/或类型信息的结果值确定。

公开(公告)号：US20130219102A1

公开(公告)日：2013-08-22

申请号：US13399678

申请日：2012-02-17

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F13/36

CPC classification number: G06F13/385

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local event ring. The configurable mesh event bus is configured with configuration information received via a configurable mesh control bus. The local event ring provides a communication path along which an event packet is communicated to each rectangular island along the local event ring. The local event ring involves event ring circuits and event ring segments. Upon each transition of a clock signal, an event packet moves through the ring from event ring segment to event ring segment. Event information and not packet data travels through the ring. The local event ring functions as a source-release ring in that only the event ring circuit that inserted the event packet onto the ring can delete the event packet from the ring.

Abstract translation: 基于岛屿的网络流处理器（IB-NFP）集成电路包括以行组织的岛屿。 可配置的网状事件总线延伸穿过岛，并配置为形成本地事件环。 配置的mesh事件总线配置有通过可配置的网状控制总线接收的配置信息。 本地事件环提供了沿着本地事件环将事件分组传送到每个矩形岛的通信路径。 本地事件环包括事件环电路和事件环段。 在时钟信号的每次转换时，事件分组通过环从事件环段移动到事件环段。 事件信息而不是分组数据通过环。 本地事件环作为源 - 释放环，仅将将事件包插入环的事件环电路可以从环中删除事件数据包。

公开(公告)号：US20130215792A1

公开(公告)日：2013-08-22

申请号：US13399613

申请日：2012-02-17

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: H04L12/56

CPC classification number: H04L49/15

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh control bus extends through the islands. The configurable mesh control bus is configurable to have a unidirectional tree structure such that configuration information passes into the integrated circuit, through a root island, through the branches of the tree structure, and to each of the other islands. The functional circuits of the islands, as well as a configurable mesh data bus of the integrated circuit, are all configured with configuration information supplied via the tree structure. In one example, the configurable control mesh bus portion of each island includes a statically configured switch and multiple half links that radiate from the switch. The static configuration is determined by hardwired tie off connections associated with the island.

Abstract translation: 基于岛屿的网络流处理器（IB-NFP）集成电路包括以行组织的岛屿。 可配置的网状控制总线延伸穿过岛。 可配置网格控制总线可配置为具有单向树结构，使得配置信息通过根岛通过树结构的分支以及其他岛屿中的每一个进入集成电路。 岛的功能电路以及集成电路的可配置的网格数据总线都配置有经由树结构提供的配置信息。 在一个示例中，每个岛的可配置控制网状总线部分包括静态配置的交换机和从交换机辐射的多个半链路。 静态配置由与岛屿相关联的硬线连接断开来确定。

公开(公告)号：US09621481B2

公开(公告)日：2017-04-11

申请号：US13399613

申请日：2012-02-17

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F13/00 ,  H04L12/933

CPC classification number: H04L49/15

Abstract: An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh control bus extends through the islands. The configurable mesh control bus is configurable to have a unidirectional tree structure such that configuration information passes into the integrated circuit, through a root island, through the branches of the tree structure, and to each of the other islands. The functional circuits of the islands, as well as a configurable mesh data bus of the integrated circuit, are all configured with configuration information supplied via the tree structure. In one example, the configurable control mesh bus portion of each island includes a statically configured switch and multiple half links that radiate from the switch. The static configuration is determined by hardwired tie off connections associated with the island.

公开(公告)号：US09344384B2

公开(公告)日：2016-05-17

申请号：US13675453

申请日：2012-11-13

Applicant: Gavin J. Stark ,  Nicolaas J. Viljoen ,  Niel Viljoen

Inventor： Gavin J. Stark ,  Nicolaas J. Viljoen ,  Niel Viljoen

IPC: H04L12/26 ,  H04L12/851 ,  H04L12/935 ,  H04L12/801

CPC classification number: H04L49/3063 ,  H04L43/00 ,  H04L43/18 ,  H04L47/2483 ,  H04L47/34

Abstract: An appliance receives packets that are part of a flow pair, each packet sharing an application protocol. The appliance determines an estimated application protocol of the packets without performing deep packet inspection on any packets. The estimated application protocol may be determined by using an application protocol estimation table. The appliance then predicts the inter-packet interval between a packet previously received by the appliance and a next packet not yet received by the appliance. The inter-packet interval may be determined by using an inter-packet interval prediction table. The appliance then preloads packet flow data in a cache before the next packet is predicted to arrive at the appliance. Upon receiving the next packet, the packet flow data is preloaded in the cache. This reduces packet processing time by removing waiting periods previously required to cache packet flow data from an external memory after receiving the next packet.

Abstract translation: 设备接收作为流对的一部分的数据包，每个数据包共享一个应用协议。 设备在不对任何数据包执行深度包检测的情况下确定数据包的估计应用协议。 估计的应用协议可以通过使用应用协议估计表来确定。 然后，设备预测由设备先前接收的分组与尚未由设备接收的下一个分组之间的分组间间隔。 可以通过使用分组间间隔预测表来确定分组间间隔。 然后，设备在下一个数据包预计到达设备之前，预先在缓存中加载数据包流数据。 在接收到下一个分组时，分组流数据被预加载在高速缓存中。 这通过在接收到下一个分组之后消除先前从外部存储器缓存分组流数据所需的等待时间来减少分组处理时间。

公开(公告)号：US09164794B2

公开(公告)日：2015-10-20

申请号：US13970599

申请日：2013-08-20

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F7/00 ,  G06F9/46

CPC classification number: G06F9/467

Abstract: A hardware prefix reduction circuit includes a plurality of levels. Each level includes an input conductor, an output conductor, and a plurality of nodes. Each node includes a buffer and a storage device that stores a digital logic level. One node further includes an inverter. Another node further includes an AND gate with two non-inverting inputs. Another node further includes an AND gate with an inverting input and a non-inverting input. One bit of an input value, such as an internet protocol address, is communicated on the input conductor. The first level of the prefix reduction circuit includes two nodes and each subsequent level includes twice as many nodes as is included in the preceding level. A digital logic level is individually programmed into each storage device. The digital logic levels stored in the storage devices determines the prefix reduction algorithm implemented by the hardware prefix reduction circuit.

Abstract translation: 硬件前缀缩减电路包括多个电平。 每个级别包括输入导体，输出导体和多个节点。 每个节点包括存储数字逻辑电平的缓冲器和存储设备。 一个节点还包括一个逆变器。 另一节点还包括具有两个同相输入的“与”门。 另一个节点还包括具有反相输入和非反相输入的与门。 诸如互联网协议地址的输入值的一位在输入指示器上传送。 前缀缩减电路的第一级包括两个节点，并且每个后续级别包括在前一级中包括的两倍的节点。 数字逻辑电平被分别编程到每个存储设备中。 存储在存储装置中的数字逻辑电平确定由硬件前缀缩减电路实现的前缀缩减算法。

公开(公告)号：US08972668B2

公开(公告)日：2015-03-03

申请号：US13675309

申请日：2012-11-13

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F12/00 ,  G06F9/46 ,  G06F9/34

CPC classification number: G06F13/287 ,  G06F7/10 ,  G06F9/34 ,  G06F9/467 ,  G06F12/00 ,  G06F13/00 ,  G06F13/4234 ,  G06F17/30 ,  Y02D10/14 ,  Y02D10/151

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs) and multiple key values from memory. Each key value indicates a single RV to be output by the TM. A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV is a key selector value. A key value is selected based upon the key selector value. A RV is selected based upon the key value. The key value is selected by a key selection circuit. The RV is selected by a result value selection circuit.

Abstract translation: 事务存储器（TM）从处理器接收总线上的查找命令。 该命令包括存储器地址，起始位位置和掩码大小。 响应该命令，TM拉动输入值（IV）。 存储器地址用于从存储器读取包含多个结果值（RV）和多个键值的单词。 每个键值表示TM输出的单个RV。 TM内的选择电路使用起始位位置和掩码大小来选择IV的一部分。 IV的部分是关键选择器值。 基于键选择器值选择键值。 基于键值选择RV。 键值由键选择电路选择。 RV由结果值选择电路选择。

公开(公告)号：US20150058551A1

公开(公告)日：2015-02-26

申请号：US13970601

申请日：2013-08-20

Applicant: Gavin J. Stark

Inventor： Gavin J. Stark

IPC: G06F9/46

CPC classification number: G06F9/467 ,  G06F15/163 ,  H04L45/745 ,  H04L45/7457

Abstract: A transactional memory (TM) includes a selectable bank of hardware algorithm prework engines, a selectable bank of hardware lookup engines, and a memory unit. The memory unit stores result values (RVs), instructions, and lookup data operands. The transactional memory receives a lookup command across a bus from one of a plurality of processors. The lookup command includes a source identification value, data, a table number value, and a table set value. In response to the lookup command, the transactional memory selects one hardware algorithm prework engine and one hardware lookup engine to perform the lookup operation. The selected hardware algorithm prework engine modifies data included in the lookup command. The selected hardware lookup engine performs a lookup operation using the modified data and lookup operands provided by the memory unit. In response to performing the lookup operation, the transactional memory returns a result value and optionally an instruction.

Abstract translation: 事务存储器（TM）包括可选择的硬件算法预处理引擎组，可选择的硬件查找引擎组和存储器单元。 存储单元存储结果值（RV），指令和查找数据操作数。 事务存储器从多个处理器之一接收总线上的查找命令。 查找命令包括源标识值，数据，表号值和表设置值。 响应于查找命令，事务存储器选择一个硬件算法预处理引擎和一个硬件查找引擎来执行查找操作。 所选的硬件算法预处理引擎修改查找命令中包含的数据。 所选择的硬件查找引擎使用由存储器单元提供的经修改的数据和查找操作数来执行查找操作。 响应于执行查找操作，事务存储器返回结果值和可选的指令。