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41.发明申请公开(公告)号：US20100225366A1
公开(公告)日：2010-09-09
申请号：US12703022
申请日：2010-02-09
CPC分类号： H03K5/1565 , H03K3/0322 , H03K5/00006
摘要： Systems and methods for design and operation of signal generator circuitry with output frequencies greater than the oscillator frequency. Accordingly, in a first method embodiment, a method of producing an output periodic electronic signal comprises accessing four signals having a quadrature phase relationship. First and second pairs of these signals having a one half cycle phase relationship are averaged to produce two signals having an improved duty cycle and a one-quarter cycle phase relationship. The first and second averaged periodic electronic signals are combined in an exclusive OR circuit to produce the output periodic electronic signal at twice the oscillator frequency. Advantageously, the periodic signal may comprise a desirable duty cycle of 50 percent.
摘要翻译： 信号发生器电路的设计和操作的系统和方法，输出频率大于振荡器频率。 因此，在第一方法实施例中，产生输出周期性电子信号的方法包括访问具有正交相位关系的四个信号。 将具有一个半周期相位关系的第一和第二对这些信号进行平均，以产生具有改善的占空比和四分之一周期相位关系的两个信号。 第一和第二平均周期性电子信号在异或电路中组合以产生两倍于振荡器频率的输出周期性电子信号。 有利地，周期信号可以包括50％的期望占空比。
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42.发明授权Memory protection and address translation hardware support for virtual machines 有权虚拟机的内存保护和地址转换硬件支持公开(公告)号：US07734892B1
公开(公告)日：2010-06-08
申请号：US11096922
申请日：2005-03-31
申请人： Guillermo J. Rozas , Nathan Laredo
发明人： Guillermo J. Rozas , Nathan Laredo
IPC分类号： G06F21/00
CPC分类号： G06F12/1036 , G06F9/45558 , G06F12/145 , G06F2009/45583
摘要： A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application on a host computer system, executing a first virtual machine application within a first virtual machine, and executing a second virtual machine application within a second virtual machine. A plurality of TLB (translation look aside buffer) entries for the first virtual machine application and the second machine application are stored within a TLB of the host computer system. At least one of the plurality of TLB entries is a global TLB entry.
摘要翻译： 一种为虚拟机提供内存保护和虚拟内存地址转换的硬件支持的方法。 该方法包括在主计算机系统上执行主机应用，在第一虚拟机内执行第一虚拟机应用，以及在第二虚拟机内执行第二虚拟机应用。 用于第一虚拟机应用和第二机器应用的多个TLB（转换后备缓冲器）条目被存储在主计算机系统的TLB内。 多个TLB条目中的至少一个是全局TLB条目。
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43.发明授权Methods and systems employing a flag for deferring exception handling to a commit or rollback point 有权使用标志将异常处理推迟到提交或回滚点的方法和系统公开(公告)号：US07310723B1
公开(公告)日：2007-12-18
申请号：US10406022
申请日：2003-04-02
IPC分类号： G06F7/499
CPC分类号： G06F9/30076 , G06F9/30101 , G06F9/30174 , G06F9/3863 , G06F9/3865
摘要： Methods and systems thereof for exception handling are described. An event to be handled is identified during execution of a code sequence. A bit is set to indicate that handling of the event is to be deferred. An exception corresponding to the event is generated if the bit is set.
摘要翻译： 描述用于异常处理的方法和系统。 在执行代码序列期间识别要处理的事件。 有一点被设置为指示事件的处理被推迟。 如果该位被置位，则会生成与该事件相对应的异常。
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44.发明授权Method and apparatus for scheduling to reduce space and increase speed of microprocessor operations 有权用于调度以减少微处理器操作的空间和增加速度的方法和装置公开(公告)号：US06738893B1
公开(公告)日：2004-05-18
申请号：US09557650
申请日：2000-04-25
申请人： Guillermo J. Rozas
发明人： Guillermo J. Rozas
IPC分类号： G06F930
CPC分类号： G06F9/3853 , G06F8/447
摘要： A process for scheduling computer processor execution of operations in a plurality of instruction word formats including the steps of arranging commands into properly formatted instruction words beginning at one end into a sequence selected to provide the most rapid execution of the operations, and then rearranging the operations within the plurality of instruction words from the other end of the sequence into instruction words selected to occupy the least space in memory.
摘要翻译： 一种用于以多种指令字格式调度计算机处理器执行操作的过程，包括以下步骤：将命令排列成从一端开始的正确格式化的指令字到被选择以提供操作的最快速执行的序列，然后重新排列操作 在多个指令字中，从序列的另一端到选择为占用存储器中的最小空间的指令字。
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公开(公告)号：US08751753B1
公开(公告)日：2014-06-10
申请号：US11102171
申请日：2005-04-07
申请人： Guillermo J. Rozas
发明人： Guillermo J. Rozas
IPC分类号： G06F13/00
CPC分类号： G06F12/0815 , G06F12/0808 , G06F12/0817 , G06F12/0822 , G06F12/0831 , G06F12/084 , G06F12/128 , G06F2212/1008 , G06F2212/1021
摘要： A coherence decoupling buffer. In accordance with a first embodiment of the present invention, a coherence decoupling buffer is for storing tag information of cache lines evicted from a plurality of cache memories. A coherence decoupling buffer may be free of value information of the plurality of cache memories. A coherence decoupling buffer may also be combined with a coherence memory.
摘要翻译： 相干解耦缓冲器。 根据本发明的第一实施例，相干解耦缓冲器用于存储从多个高速缓冲存储器中逐出的高速缓存线的标签信息。 相干解耦缓冲器可以没有多个高速缓冲存储器的值信息。 相干解耦缓冲器也可以与相干存储器组合。
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46.发明授权Setting a flag bit to defer event handling to one of multiple safe points in an instruction stream 有权设置标志位将事件处理延迟到指令流中的多个安全点之一公开(公告)号：US08464033B2
公开(公告)日：2013-06-11
申请号：US13221812
申请日：2011-08-30
IPC分类号： G06F9/00
CPC分类号： G06F9/30076 , G06F9/30101 , G06F9/30174 , G06F9/3863 , G06F9/3865
摘要： Methods and systems thereof for exception handling are described. An event to be handled is identified during execution of a code sequence. A bit is set to indicate that handling of the event is to be deferred. An exception corresponding to the event is generated if the bit is set.
摘要翻译： 描述用于异常处理的方法和系统。 在执行代码序列期间识别要处理的事件。 有一点被设置为指示事件的处理被推迟。 如果该位被置位，则会生成与事件相对应的异常。
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公开(公告)号：US07793347B2
公开(公告)日：2010-09-07
申请号：US11053080
申请日：2005-02-07
申请人： Guillermo J. Rozas
发明人： Guillermo J. Rozas
IPC分类号： G06F11/00
CPC分类号： G06F21/57
摘要： Validating a computer system. An integrity check program is declared during booting of the computer system. It is determined whether the integrity check program quasi-periodically validates dynamic data structures of an operating system within a time interval.
摘要翻译： 验证计算机系统。 在计算机系统引导期间声明完整性检查程序。 确定完整性检查程序是否在一段时间间隔内准确地周期性地验证操作系统的动态数据结构。
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48.发明授权公开(公告)号：US07696797B1
公开(公告)日：2010-04-13
申请号：US11540387
申请日：2006-09-29
IPC分类号： H03L7/06
CPC分类号： H03K5/1565 , H03K3/0322 , H03K5/00006
摘要： Systems and methods for design and operation of signal generator circuitry with output frequencies greater than the oscillator frequency. Accordingly, in a first method embodiment, a method of producing an output periodic electronic signal comprises accessing four signals having a quadrature phase relationship. First and second pairs of these signals having a one half cycle phase relationship are averaged to produce two signals having an improved duty cycle and a one-quarter cycle phase relationship. The first and second averaged periodic electronic signals are combined in an exclusive OR circuit to produce the output periodic electronic signal at twice the oscillator frequency. Advantageously, the periodic signal may comprise a desirable duty cycle of 50 percent.
摘要翻译： 信号发生器电路的设计和操作的系统和方法，输出频率大于振荡器频率。 因此，在第一方法实施例中，产生输出周期性电子信号的方法包括访问具有正交相位关系的四个信号。 将具有一个半周期相位关系的这些信号的第一和第二对平均以产生具有改善的占空比和四分之一周期相位关系的两个信号。 第一和第二平均周期性电子信号在异或电路中组合以产生两倍于振荡器频率的输出周期性电子信号。 有利地，周期信号可以包括50％的期望占空比。
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公开(公告)号：US07620779B1
公开(公告)日：2009-11-17
申请号：US11439361
申请日：2006-05-22
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, it signals the external agent to proceed with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.
摘要翻译： 有效处理直接存储器访问请求的方法和系统。 外部代理从目标地址的计算机系统的存储系统请求数据。 侦听缓存确定目标地址是否在已知对外部访问安全的地址范围内。 如果窥探缓存确定目标地址是安全的，则它会通知外部代理继续直接访问内存。 如果侦听缓存不能确定目标地址是否安全，则侦听缓存将请求转发到处理器。 在处理器解决其本身与存储器系统之间的任何一致性问题之后，处理器发信号通知外部代理进行直接存储器访问。 监听缓存可以确定这种处理器活动的安全地址范围。 监听缓存通过观察处理器和存储系统之间的流量来使其安全地址范围无效。
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公开(公告)号：US07089404B1
公开(公告)日：2006-08-08
申请号：US09332338
申请日：1999-06-14
CPC分类号： G06F9/30174 , G06F9/3808 , G06F9/3834 , G06F9/3836 , G06F9/3863
摘要： Apparatus and a method for causing scheduler software to produce code which executes more rapidly by ignoring some of the normal constraints placed on its scheduling operations and simply scheduling certain instructions to run as fast as possible, raising an exception if the scheduling violates a scheduling constraint, and determining steps to be taken for correctly executing each set of instructions about which an exception is raised.
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