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公开(公告)号：US07089404B1
公开(公告)日：2006-08-08
申请号：US09332338
申请日：1999-06-14
CPC分类号： G06F9/30174 , G06F9/3808 , G06F9/3834 , G06F9/3836 , G06F9/3863
摘要： Apparatus and a method for causing scheduler software to produce code which executes more rapidly by ignoring some of the normal constraints placed on its scheduling operations and simply scheduling certain instructions to run as fast as possible, raising an exception if the scheduling violates a scheduling constraint, and determining steps to be taken for correctly executing each set of instructions about which an exception is raised.
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2.发明授权公开(公告)号：US09081563B2
公开(公告)日：2015-07-14
申请号：US13488138
申请日：2012-06-04
CPC分类号： G06F9/30174 , G06F9/3808 , G06F9/3834 , G06F9/3836 , G06F9/3863
摘要： Apparatus and a method for causing scheduler software to produce code which executes more rapidly by ignoring some of the normal constraints placed on its scheduling operations and simply scheduling certain instructions to run as fast as possible, raising an exception if the scheduling violates a scheduling constraint, and determining steps to be taken for correctly executing each set of instructions about which an exception is raised.
摘要翻译： 用于使调度器软件产生代码的装置和方法，所述代码通过忽略放置在其调度操作上的一些正常约束并且简单地调度某些指令以尽可能快地运行来更快地执行，如果调度违反调度约束，则引发异常， 以及确定要正确执行引发异常的每组指令的步骤。
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3.发明申请公开(公告)号：US20120246453A1
公开(公告)日：2012-09-27
申请号：US13488138
申请日：2012-06-04
IPC分类号： G06F9/38
CPC分类号： G06F9/30174 , G06F9/3808 , G06F9/3834 , G06F9/3836 , G06F9/3863
摘要： Apparatus and a method for causing scheduler software to produce code which executes more rapidly by ignoring some of the normal constraints placed on its scheduling operations and simply scheduling certain instructions to run as fast as possible, raising an exception if the scheduling violates a scheduling constraint, and determining steps to be taken for correctly executing each set of instructions about which an exception is raised.
摘要翻译： 用于使调度器软件产生代码的装置和方法，所述代码通过忽略放置在其调度操作上的一些正常约束并且简单地调度某些指令以尽可能快地运行来更快地执行，如果调度违反调度约束，则引发异常， 以及确定要正确执行引发异常的每组指令的步骤。
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4.发明授权公开(公告)号：US08209517B1
公开(公告)日：2012-06-26
申请号：US10783473
申请日：2004-02-20
CPC分类号： G06F9/30174 , G06F9/3808 , G06F9/3834 , G06F9/3836 , G06F9/3863
摘要： Apparatus and a method for causing scheduler software to produce code which executes more rapidly by ignoring some of the normal constraints placed on its scheduling operations and simply scheduling certain instructions to run as fast as possible, raising an exception if the scheduling violates a scheduling constraint, and determining steps to be taken for correctly executing each set of instructions about which an exception is raised.
摘要翻译： 用于使调度器软件产生代码的装置和方法，所述代码通过忽略放置在其调度操作上的一些正常约束并且简单地调度某些指令以尽可能快地运行来更快地执行，如果调度违反调度约束，则引发异常， 以及确定要正确执行引发异常的每组指令的步骤。
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公开(公告)号：US06571316B1
公开(公告)日：2003-05-27
申请号：US09595077
申请日：2000-06-16
申请人： Godfrey P. D'Souza , Paul S. Serris
发明人： Godfrey P. D'Souza , Paul S. Serris
IPC分类号： G06F1206
CPC分类号： G06F9/342 , G06F9/3802 , G06F12/0875
摘要： Apparatus including a cache having a plurality of storage positions for data and for addresses, each of the storage positions including in the storage positions signifying one of a plurality of address spaces; and selection circuitry selecting data from a storage position based on an address including an address space indicator.
摘要翻译： 一种装置，包括具有多个用于数据和地址的存储位置的高速缓存，每个存储位置包括表示多个地址空间中的一个的存储位置; 以及选择电路基于包括地址空间指示符的地址从存储位置选择数据。
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公开(公告)号：US20100011233A1
公开(公告)日：2010-01-14
申请号：US12502685
申请日：2009-07-14
申请人： Sameer Halepete , H. Peter Anvin , Zongjian Chen , Godfrey P. D'Souza , Marc Fleischmann , Keith Klayman , Thomas Lawrence , Andrew Read
发明人： Sameer Halepete , H. Peter Anvin , Zongjian Chen , Godfrey P. D'Souza , Marc Fleischmann , Keith Klayman , Thomas Lawrence , Andrew Read
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.
摘要翻译： 一种用于控制计算机使用的功率的方法，包括以下步骤：测量计算机的中央处理器的操作特性，确定中央处理器的操作特性何时与正在进行的操作所要求的显着不同，以及改变操作 中央处理器的特性与正在进行的操作相当。
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公开(公告)号：US5606270A
公开(公告)日：1997-02-25
申请号：US357607
申请日：1994-12-16
IPC分类号： H03K3/356 , H03K19/00 , H03K19/096 , H03K19/20
CPC分类号： H03K19/0963 , H03K19/0016
摘要： A dynamic clocked inverter latch with reduced charge leakage includes a first node biasing circuit with a P-MOSFET and an N-MOSFET totem-pole-coupled between VDD and an output node, and a second node biasing circuit with another N-MOSFET and another P-MOSFET totem-pole-coupled between the output node and VSS. The first P-MOSFET receives an input data signal and the first N-MOSFET receives a clock signal and in accordance therewith together cause the output node to charge to a charged state having a charge voltage associated therewith. The second N-MOSFET also receives the input data signal while the second P-MOSFET receives the inverse of the clock signal and in accordance therewith together cause the output node to discharge to a discharged state having a discharge voltage associated therewith. During inactive states of the clock signal, the first N-MOSFET becomes reverse-biased by the output node discharge voltage, while during inactive states of the inverse clock signal, the second P-MOSFET becomes reverse-biased by the output node charge voltage, thereby virtually eliminating charge leakage to and from the output node, respectively.
摘要翻译： 具有减小的电荷泄漏的动态时钟反相器锁存器包括具有P-MOSFET的第一节点偏置电路和VDD与输出节点之间的N-MOSFET图腾柱耦合，以及具有另一N-MOSFET和另一N-MOSFET的第二节点偏置电路 输出节点和VSS之间的P-MOSFET图腾柱耦合。 第一P-MOSFET接收输入数据信号，并且第一N-MOSFET接收时钟信号，并且根据它们一起导致输出节点充电到具有与其相关联的充电电压的充电状态。 第二N-MOSFET还接收输入数据信号，而第二P-MOSFET接收到时钟信号的反相，并且根据它们一起使得输出节点放电到具有与其相关联的放电电压的放电状态。 在时钟信号的非活动状态期间，第一N-MOSFET由输出节点放电电压反向偏置，而在反时钟信号的非活动状态期间，第二P-MOSFET由输出节点充电电压反向偏置， 从而实际上分别消除了来自输出节点的电荷泄漏。
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8.发明授权
公开(公告)号：US5583821A
公开(公告)日：1996-12-10
申请号：US509599
申请日：1995-07-31
IPC分类号： G11C11/412 , G11C11/404 , G11C11/407 , G11C11/418 , G11C7/00
CPC分类号： G11C11/404 , G11C11/418
摘要： A storage cell includes a first bit line, a storage circuit, and a pass transistor. The storage circuit has a first storage node for holding a logic state indicative of a logic value. The pass transistor is coupled to the first bit line and the first storage node for establishing a conduction path therebetween. The pass transistor receives a bias voltage to switch the pass transistor into a substantially nonconducting state when the storage cell is not being accessed. The reverse bias on the first transistor substantially reduces the leakage current through the pass transistor.
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公开(公告)号：US20090072858A1
公开(公告)日：2009-03-19
申请号：US11855666
申请日：2007-09-14
申请人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
发明人： Godfrey P. D'Souza , Douglas Laird , Malcolm J. Wing , Colin N. Murphy , Dana L. How , Robert Yu , Jay B. Patel , Ivo Dobbelaere , Jason Golbus , Suresh Subramaniam , Mukunda Krishnappa , Pohrong R. Chu , Dave Trossen , Kevin James
IPC分类号： H03K19/173
CPC分类号： H03K19/177
摘要： A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.
摘要翻译： 一种包括多个可编程逻辑块，多个特殊用途块和可操作地连接多个可编程逻辑块和多个专用块的可配置高速网状互连结构的系统，其中可配置的高速 网状互连结构被配置为实现横跨系统的多个互连管线总线。
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公开(公告)号：US07100061B2
公开(公告)日：2006-08-29
申请号：US09484516
申请日：2000-01-18
申请人： Sameer Halepete , H. Peter Anvin , Zongjian Chen , Godfrey P. D'Souza , Marc Fleischmann , Keith Klayman , Thomas Lawrence , Andrew Read
发明人： Sameer Halepete , H. Peter Anvin , Zongjian Chen , Godfrey P. D'Souza , Marc Fleischmann , Keith Klayman , Thomas Lawrence , Andrew Read
IPC分类号： G06F1/30
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.
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