公开(公告)号：US20210001635A1

公开(公告)日：2021-01-07

申请号：US16977675

申请日：2018-12-03

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： James Michael GARDNER ,  Scott A. LINN ,  Stephen D. PANSHIN ,  Jefferson P. WARD ,  David Owen ROETHIG

IPC: B41J2/175 ,  G06F21/85 ,  G06F21/44 ,  G06F21/74

Abstract: In an example, a logic circuit comprising a communications interface including a data contact to communicate via a communications bus, an enablement contact, separate from the communication interface, to receive an input to enable the logic circuit, and at least one memory register, comprising at least one reconfigurable address register. The logic circuit may be configured, such that, when enabled, it responds to communications sent via the communication bus which are addressed to the address held in a reconfigurable address register.

公开(公告)号：US20200174963A1

公开(公告)日：2020-06-04

申请号：US16781052

申请日：2020-02-04

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Stephen D. PANSHIN ,  Scott A. LINN

IPC: G06F13/42 ,  B41J2/175 ,  G03G21/18

Abstract: Logic circuitry packages for association with replaceable print apparatus components are disclosed herein. An example logic circuitry package includes a timer and a serial data bus interface including a data contact and a clock contact, the serial data bus interface to interface with a serial data bus of a printer. The example logic circuitry package also includes logic circuitry to, in response to a first command sent to the logic circuitry package via the serial data bus of the printer: initiate a low voltage on the data contact; wait for a time period tracked by the timer to expire, without reference to a clock signal at the clock contact from the serial data bus; and upon expiration of the time period, cause the data contact to assume a second voltage different than the low voltage. The first command specifies a duration of the time period and the example logic circuitry is to maintain the low voltage on the data contact based on the duration of the time period.

公开(公告)号：US20230074257A1

公开(公告)日：2023-03-09

申请号：US17985590

申请日：2022-11-11

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Scott A. LINN ,  James Michael GARDNER ,  Erik D. NESS

IPC: B41J2/045

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of first non-volatile memory cells and control logic. Each first non-volatile memory cell stores a customization bit. The control logic configures an operation of the integrated circuit based on the customization bits.

公开(公告)号：US20220349872A1

公开(公告)日：2022-11-03

申请号：US17865253

申请日：2022-07-14

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： John Rossi ,  Scott A. LINN ,  James Michael GARDNER ,  Erik D. NESS

IPC: G01N33/49 ,  A61K47/18 ,  A61K47/26 ,  G01N27/327 ,  G01N33/66

Abstract: A fluid ejection controller interface includes input logic to receive control data packets and a first clock signal, each control data packet including a set of primitive data bits and a set of random bits, wherein the input logic identifies the random bits in the received control data packets to facilitate the creation of modified control data packets. The fluid ejection controller interface includes a clock signal generator to generate a second clock signal that is different than the first clock signal, and output logic to receive the modified control data packets, and output the modified control data packets to a fluid ejection controller of a fluid ejection device based on the second clock signal.

公开(公告)号：US20210334391A1

公开(公告)日：2021-10-28

申请号：US16495227

申请日：2018-12-03

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： James Michael GARDNER ,  Scott A. LINN ,  Stephen D. PANSHIN ,  Jefferson P. WARD ,  David Owen ROETHIG

IPC: G06F21/60 ,  G06F13/42 ,  G06F21/44 ,  B41J2/175

Abstract: In an example, a method comprises, by logic circuitry associated with a replaceable print apparatus component, responding to a first validation request sent via an I2C bus to a first address associated with the logic circuitry with a first validation response; and responding to a second validation request sent via the I2C bus to a second address associated with the logic circuitry with a second validation response.

公开(公告)号：US20210326296A1

公开(公告)日：2021-10-21

申请号：US17364027

申请日：2021-06-30

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Stephen D. PANSHIN ,  Scott A. LINN

IPC: G06F13/42 ,  B41J2/175 ,  G03G21/18 ,  G06F13/38 ,  H04N1/00

Abstract: An example replaceable print material supply cartridge that is removably couplable to a host printer is disclosed. The example replaceable print material supply cartridge includes an ink reservoir and a logic circuitry package. The logic circuitry package includes logic circuitry and a serial data bus interface, wherein the serial data bus interface is to interface with a serial data bus of the host printer. In response to a first command sent to the logic circuitry package via the serial data bus connected to the serial data bus interface, the first command including a time period, the logic circuitry is to cause generation of a low voltage condition on the serial data bus for a duration based on the time period, and, after the duration, cause a return to a default voltage condition on the serial data bus.

公开(公告)号：US20210229426A1

公开(公告)日：2021-07-29

申请号：US16957517

申请日：2019-02-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Scott A. LINN ,  James Michael GARDNER ,  Michael W. CUMBIE

IPC: B41J2/045

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of first memory cells, a plurality of first storage elements, and control logic. Each first memory cell stores a customization bit. Each first storage element is coupled to a corresponding first memory cell. The control logic, in response to a reset signal, reads the customization bit stored in each first memory cell and latches each customization bit in a corresponding first storage element.

公开(公告)号：US20210221128A1

公开(公告)日：2021-07-22

申请号：US16772522

申请日：2019-02-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： James M. GARDNER ,  George H. CORRIGAN ,  Scott A. LINN

IPC: B41J2/045

Abstract: An integrated circuit to drive a plurality of fluid actuators is disclosed. The integrated circuit analog delay circuits coupled in series and to a fire input to receive a fire signal in succession. Each analog delay circuit receives the fire signal and, after a delay, provides the fire signal via an output to a corresponding fluid actuator. A bias circuit is coupled to each of the of analog delay circuits. The bias circuit provides a bias signal to control the delay.

公开(公告)号：US20210221120A1

公开(公告)日：2021-07-22

申请号：US16768023

申请日：2019-02-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Scott A. LINN ,  James Michael GARDNER ,  Michael W. CUMBIE

IPC: B41J2/045

Abstract: An integrated circuit for a fluidic die including an address bus to communicate a set of addresses, a first group of die configuration functions including a first address driver to drive a first portion of an address of the set of addresses on the address bus, a second group of die configuration functions including a second address driver to drive a second portion of the address of the set of addresses on the address bus, and an array of fluid actuating devices addressable by the set of addresses communicated via the address bus.

公开(公告)号：US20210213746A1

公开(公告)日：2021-07-15

申请号：US16767582

申请日：2019-10-25

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： James Michael GARDNER ,  Sirena LU ,  Scott A. LINN

IPC: B41J2/175 ,  G06F13/42 ,  B41J2/045

Abstract: A logic circuitry package for a replaceable print apparatus component includes a first at least one analog cell of a first type, a second at least one analog cell of a second type, an analog-digital converter (ADC), an interface to communicate with a print apparatus logic circuit, and at least one logic circuit. The at least one logic circuit is configured to receive, via the interface, requests to perform measurements to selected ones of the at least one first and second analog cells. The at least one logic circuit is configured to selectively route analog signals from the selected analog cells to the ADC based on the requests.