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公开(公告)号：US20080239834A1
公开(公告)日：2008-10-02
申请号：US11942665
申请日：2007-11-19
CPC分类号： G11C11/5642 , G11C7/06 , G11C7/062
摘要： A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.
摘要翻译： 存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。 读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。 比较器的第一输入耦合到低阻抗电路和参考电压节点。 比较器的第二输入耦合到数据电压节点。 第一负载电路加载耦合到参考电压节点的参考电池。 第二负载电路加载耦合到数据电压节点的数据单元。
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42.发明授权Method of programming a split gate non-volatile floating gate memory cell having a separate erase gate 有权编程具有单独的擦除栅极的分离栅极非易失性浮动栅极存储单元的方法公开(公告)号：US08488388B2
公开(公告)日：2013-07-16
申请号：US13286933
申请日：2011-11-01
申请人： Viktor Markov , Jong-Won Yoo , Hung Quoc Nguyen , Alexander Kotov
发明人： Viktor Markov , Jong-Won Yoo , Hung Quoc Nguyen , Alexander Kotov
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： G11C16/0416 , G11C16/3418 , H01L21/28273 , H01L29/42328
摘要： A non-volatile memory cell includes first and second regions and a channel region therebetween, a word line gate over a first portion of the channel region, a floating gate over another portion of the channel region and adjacent to the word line gate, a coupling gate over the floating gate, and an erase gate adjacent to the floating gate on an opposite side to the word line gate and over the second region. Programming the memory cell includes applying a first positive voltage to the word line gate, applying a voltage differential between the first and second regions, applying a second positive voltage to the coupling gate (where the voltages and the voltage differential are applied substantially at the same time), and applying a third positive voltage to the erase gate after a period of delay from the application of the first and second positive voltages and the voltage differential.
摘要翻译： 非易失性存储单元包括第一和第二区域以及它们之间的沟道区域，沟道区域的第一部分上的字线栅极，沟道区域的另一部分上的浮动栅极，并且与字线栅极相邻，耦合 在浮动栅极上方的栅极，以及与该字线栅极相反侧和第二区域上方的浮动栅极相邻的擦除栅极。 对存储器单元进行编程包括对第一和第二区域施加第一正电压到第一和第二区域之间施加第一正电压，向耦合栅极施加第二正电压（其中施加电压和电压差异基本相同 时间），并且在施加第一和第二正电压和电压差之后延迟一段时间后，向擦除栅极施加第三正电压。
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43.发明申请Method Of Programming A Split Gate Non-volatile Floating Gate Memory Cell Having A Separate Erase Gate 有权具有独立擦除门的分离门非易失性浮动栅极存储单元的编程方法公开(公告)号：US20130107631A1
公开(公告)日：2013-05-02
申请号：US13286933
申请日：2011-11-01
申请人： Viktor Markov , Jong-Won Yoo , Hung Quoc Nguyen , Alexander Kotov
发明人： Viktor Markov , Jong-Won Yoo , Hung Quoc Nguyen , Alexander Kotov
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/3418 , H01L21/28273 , H01L29/42328
摘要： A non-volatile memory cell includes first and second regions and a channel region therebetween, a word line gate over a first portion of the channel region, a floating gate over another portion of the channel region and adjacent to the word line gate, a coupling gate over the floating gate, and an erase gate adjacent to the floating gate on an opposite side to the word line gate and over the second region. Programming the memory cell includes applying a first positive voltage to the word line gate, applying a voltage differential between the first and second regions, applying a second positive voltage to the coupling gate (where the voltages and the voltage differential are applied substantially at the same time), and applying a third positive voltage to the erase gate after a period of delay from the application of the first and second positive voltages and the voltage differential.
摘要翻译： 非易失性存储单元包括第一和第二区域以及它们之间的沟道区域，沟道区域的第一部分上的字线栅极，沟道区域的另一部分上的浮动栅极，并且与字线栅极相邻，耦合 在浮动栅极上方的栅极，以及与该字线栅极相反侧和第二区域上方的浮动栅极相邻的擦除栅极。 对存储器单元进行编程包括对第一和第二区域施加第一正电压到第一和第二区域之间施加第一正电压，向耦合栅极施加第二正电压（其中施加电压和电压差异基本相同 时间），并且在施加第一和第二正电压和电压差之后延迟一段时间后，向擦除栅极施加第三正电压。
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公开(公告)号：US11231078B2
公开(公告)日：2022-01-25
申请号：US14828420
申请日：2015-08-17
申请人： Hung Quoc Nguyen
发明人： Hung Quoc Nguyen
IPC分类号： F16D57/00 , F16D121/20
摘要： A method and apparatus for an automobile's magneto-rheological brake (MRB) are disclosed which include: a shaft connected to a stationary housing, a magneto-rheological fluid chamber positioned inside the stationary housing, a rotary disc connected to and rotate with the shaft, a plurality of magnetic coils wound directly onto a lateral side of the MRB chamber.
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公开(公告)号：US20110103258A1
公开(公告)日：2011-05-05
申请号：US12610044
申请日：2009-10-30
IPC分类号： H04L12/28
CPC分类号： H04L41/0893 , H04L41/12 , H04L49/00 , H04L49/357 , H04L61/6045 , H04L67/1097
摘要： Subsets of isolated communications networks are selectively merged without merging the entire isolated communications networks, and devices are imported across isolated communications networks without merging the isolated communications networks. The presently disclosed technology provides for improved scalability, performance, and security in logical networks spanning two or more physical communications networks.
摘要翻译： 隔离通信网络的子集选择性地合并而不合并整个隔离的通信网络，并且设备在隔离的通信网络中导入，而不会合并隔离的通信网络。 目前公开的技术提供跨越两个或多个物理通信网络的逻辑网络中的改进的可扩展性，性能和安全性。
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46.发明申请公开(公告)号：US20100315112A1
公开(公告)日：2010-12-16
申请号：US12775126
申请日：2010-05-06
CPC分类号： G01R1/0466 , G01R1/0491
摘要： An integrated probe card and socket adapter includes probe needles for probing a wafer including a plurality of CSP IC each having a plurality of bumps. A socket adapter includes a socket body having an elevated portion and a recessed base portion. The recessed base portion has a base portion thickness and includes a plurality of base portion through-holes that align with and receive the bumps on at least one of said plurality of CSP IC after singulation (singulated CSP IC) for securing the singulated CSP IC thereto. The elevated portion includes a plurality of elevated portion through-holes for fastening to the probe card when the probe card is underlying. The base portion thickness is sized so that the probe needles extend into the base portion through-holes a sufficient distance to contact the bumps of the singulated CSP IC for testing using the probe card.
摘要翻译： 集成探针卡和插座适配器包括探针，用于探测包括多个CSP IC的晶片，每个CSP IC具有多个凸块。 插座适配器包括具有升高部分和凹入基部的插座本体。 凹形基部具有基部厚度，并且包括多个基准部分通孔，所述多个基部通孔在分割后的所述多个CSP IC中的至少一个CSP IC上对齐并接收用于将单个CSP IC固定的单个CSP IC 。 升高部分包括多个提升部分通孔，用于当探针卡处于底部时用于紧固到探针卡。 基部部分厚度的尺寸设定成使得探针能够延伸到基部通孔中足够的距离以接触单个CSP IC的凸块，以便使用探针卡进行测试。
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公开(公告)号：US08817804B2
公开(公告)日：2014-08-26
申请号：US12610044
申请日：2009-10-30
CPC分类号： H04L41/0893 , H04L41/12 , H04L49/00 , H04L49/357 , H04L61/6045 , H04L67/1097
摘要： Subsets of isolated communications networks are selectively merged without merging the entire isolated communications networks, and devices are imported across isolated communications networks without merging the isolated communications networks. The presently disclosed technology provides for improved scalability, performance, and security in logical networks spanning two or more physical communications networks.
摘要翻译： 隔离通信网络的子集选择性地合并而不合并整个隔离的通信网络，并且设备在隔离的通信网络中导入，而不会合并隔离的通信网络。 目前公开的技术提供跨越两个或多个物理通信网络的逻辑网络中的改进的可扩展性，性能和安全性。
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