公开(公告)号：US08576648B2

公开(公告)日：2013-11-05

申请号：US13293056

申请日：2011-11-09

申请人： Viktor Markov ,  Jong-Won Yoo ,  Satish Bansal ,  Alexander Kotov

发明人： Viktor Markov ,  Jong-Won Yoo ,  Satish Bansal ,  Alexander Kotov

IPC分类号： G11C7/00 ,  G11C29/50

CPC分类号： G11C29/50 ,  G11C16/00 ,  G11C16/349 ,  G11C29/06 ,  G11C29/50004 ,  G11C29/50016

摘要： A method of decreasing the test time to determine data retention (e.g. leakage current) of a memory cell having a floating gate for the storage of charges thereon. The memory cell is characterized by the leakage current having a rate of leakage which is dependent upon the absolute value of the voltage of the floating gate. The memory cell is further characterized by a first erase voltage and a first programming voltage, applied during normal operation, and a first read current detected during normal operation. The method applies a voltage greater than the first erase voltage or greater than the first programming voltage, to over erase the floating gate. The memory cell including the floating gate is subject to a single high temperature bake. The memory cell is then tested for data retention of the floating gate based on the single high temperature bake.

摘要翻译： 一种减少测试时间以确定具有用于存储电荷的浮动栅极的存储单元的数据保持（例如泄漏电流）的方法。 存储单元的特征在于泄漏电流具有取决于浮动栅极的电压的绝对值的泄漏速率。 存储单元的特征还在于在正常操作期间施加的第一擦除电压和第一编程电压以及在正常操作期间检测到的第一读取电流。 该方法施加大于第一擦除电压或大于第一编程电压的电压，以过度擦除浮置栅极。 包括浮动栅极的存储单元经受单次高温烘烤。 然后基于单个高温烘烤来测试存储器单元的浮动栅极的数据保持。

公开(公告)号：US20130114337A1

公开(公告)日：2013-05-09

申请号：US13293056

申请日：2011-11-09

申请人： Viktor Markov ,  Jong-Won Yoo ,  Satish Bansal ,  Alexander Kotov

发明人： Viktor Markov ,  Jong-Won Yoo ,  Satish Bansal ,  Alexander Kotov

IPC分类号： G11C16/04

CPC分类号： G11C29/50 ,  G11C16/00 ,  G11C16/349 ,  G11C29/06 ,  G11C29/50004 ,  G11C29/50016

摘要： A method of decreasing the test time to determine data retention (e.g. leakage current) of a memory cell having a floating gate for the storage of charges thereon. The memory cell is characterized by the leakage current having a rate of leakage which is dependent upon the absolute value of the voltage of the floating gate. The memory cell is further characterized by a first erase voltage and a first programming voltage, applied during normal operation, and a first read current detected during normal operation. The method applies a voltage greater than the first erase voltage or greater than the first programming voltage, to over erase the floating gate. The memory cell including the floating gate is subject to a single high temperature bake. The memory cell is then tested for data retention of the floating gate based on the single high temperature bake.

摘要翻译： 一种减少测试时间以确定具有用于存储电荷的浮动栅极的存储单元的数据保持（例如泄漏电流）的方法。 存储单元的特征在于泄漏电流具有取决于浮动栅极的电压的绝对值的泄漏速率。 存储单元的特征还在于在正常操作期间施加的第一擦除电压和第一编程电压以及在正常操作期间检测到的第一读取电流。 该方法施加大于第一擦除电压或大于第一编程电压的电压，以过度擦除浮置栅极。 包括浮动栅极的存储单元经受单次高温烘烤。 然后基于单个高温烘烤来测试存储器单元的浮动栅极的数据保持。

公开(公告)号：US07927994B1

公开(公告)日：2011-04-19

申请号：US12961193

申请日：2010-12-06

申请人： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

发明人： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

IPC分类号： H01L21/4763

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

摘要翻译： 改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间 和底物中的第二区域。 单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

公开(公告)号：US20090039410A1

公开(公告)日：2009-02-12

申请号：US11834574

申请日：2007-08-06

申请人： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

发明人： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

IPC分类号： H01L29/788

CPC分类号： H01L29/42328 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

摘要翻译： 改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间 和底物中的第二区域。 单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

公开(公告)号：US20110127599A1

公开(公告)日：2011-06-02

申请号：US13023443

申请日：2011-02-08

申请人： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

发明人： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

IPC分类号： H01L29/788

CPC分类号： H01L29/42328 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883

摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

摘要翻译： 改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间 和底物中的第二区域。 单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

公开(公告)号：US20100054043A1

公开(公告)日：2010-03-04

申请号：US12618632

申请日：2009-11-13

申请人： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

发明人： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

IPC分类号： G11C16/04 ,  H01L21/336 ,  G11C11/34 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

摘要翻译： 改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间 和底物中的第二区域。 单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。

公开(公告)号：US08488388B2

公开(公告)日：2013-07-16

申请号：US13286933

申请日：2011-11-01

申请人： Viktor Markov ,  Jong-Won Yoo ,  Hung Quoc Nguyen ,  Alexander Kotov

发明人： Viktor Markov ,  Jong-Won Yoo ,  Hung Quoc Nguyen ,  Alexander Kotov

IPC分类号： G11C16/04 ,  H01L29/788

CPC分类号： G11C16/0416 ,  G11C16/3418 ,  H01L21/28273 ,  H01L29/42328

摘要： A non-volatile memory cell includes first and second regions and a channel region therebetween, a word line gate over a first portion of the channel region, a floating gate over another portion of the channel region and adjacent to the word line gate, a coupling gate over the floating gate, and an erase gate adjacent to the floating gate on an opposite side to the word line gate and over the second region. Programming the memory cell includes applying a first positive voltage to the word line gate, applying a voltage differential between the first and second regions, applying a second positive voltage to the coupling gate (where the voltages and the voltage differential are applied substantially at the same time), and applying a third positive voltage to the erase gate after a period of delay from the application of the first and second positive voltages and the voltage differential.

摘要翻译： 非易失性存储单元包括第一和第二区域以及它们之间的沟道区域，沟道区域的第一部分上的字线栅极，沟道区域的另一部分上的浮动栅极，并且与字线栅极相邻，耦合 在浮动栅极上方的栅极，以及与该字线栅极相反侧和第二区域上方的浮动栅极相邻的擦除栅极。 对存储器单元进行编程包括对第一和第二区域施加第一正电压到第一和第二区域之间施加第一正电压，向耦合栅极施加第二正电压（其中施加电压和电压差异基本相同 时间），并且在施加第一和第二正电压和电压差之后延迟一段时间后，向擦除栅极施加第三正电压。

公开(公告)号：US20130107631A1

公开(公告)日：2013-05-02

申请号：US13286933

申请日：2011-11-01

申请人： Viktor Markov ,  Jong-Won Yoo ,  Hung Quoc Nguyen ,  Alexander Kotov

发明人： Viktor Markov ,  Jong-Won Yoo ,  Hung Quoc Nguyen ,  Alexander Kotov

IPC分类号： G11C16/04

CPC分类号： G11C16/0416 ,  G11C16/3418 ,  H01L21/28273 ,  H01L29/42328

摘要： A non-volatile memory cell includes first and second regions and a channel region therebetween, a word line gate over a first portion of the channel region, a floating gate over another portion of the channel region and adjacent to the word line gate, a coupling gate over the floating gate, and an erase gate adjacent to the floating gate on an opposite side to the word line gate and over the second region. Programming the memory cell includes applying a first positive voltage to the word line gate, applying a voltage differential between the first and second regions, applying a second positive voltage to the coupling gate (where the voltages and the voltage differential are applied substantially at the same time), and applying a third positive voltage to the erase gate after a period of delay from the application of the first and second positive voltages and the voltage differential.

摘要翻译： 非易失性存储单元包括第一和第二区域以及它们之间的沟道区域，沟道区域的第一部分上的字线栅极，沟道区域的另一部分上的浮动栅极，并且与字线栅极相邻，耦合 在浮动栅极上方的栅极，以及与该字线栅极相反侧和第二区域上方的浮动栅极相邻的擦除栅极。 对存储器单元进行编程包括对第一和第二区域施加第一正电压到第一和第二区域之间施加第一正电压，向耦合栅极施加第二正电压（其中施加电压和电压差异基本相同 时间），并且在施加第一和第二正电压和电压差之后延迟一段时间后，向擦除栅极施加第三正电压。

公开(公告)号：US07868375B2

公开(公告)日：2011-01-11

申请号：US12618632

申请日：2009-11-13

申请人： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien Sheng Su ,  Yaw Wen Hu

发明人： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien Sheng Su ,  Yaw Wen Hu

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

公开(公告)号：US20110076816A1

公开(公告)日：2011-03-31

申请号：US12961193

申请日：2010-12-06

申请人： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

发明人： Xian Liu ,  Amitay Levi ,  Alexander Kotov ,  Yuri Tkachev ,  Viktor Markov ,  James Yingbo Jia ,  Chien-Sheng Su ,  Yaw Wen Hu

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

摘要： An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the first region and the second region in the substrate. The cell has a select gate above a portion of the channel region, a floating gate over another portion of the channel region, a control gate above the floating gate and an erase gate adjacent to the floating gate. The erase gate has an overhang extending over the floating gate. The ratio of the dimension of the overhang to the dimension of the vertical separation between the floating gate and the erase gate is between approximately 1.0 and 2.5, which improves erase efficiency.

摘要翻译： 改进的分裂门非易失性存储单元是在具有第二导电类型的第一区域和第二导电类型的第二区域的第一导电类型的基本单晶衬底中形成的，第一区域在第一区域之间 和底物中的第二区域。 单元在通道区域的一部分上方具有选择栅极，在沟道区域的另一部分上方的浮动栅极，浮置栅极上方的控制栅极和与浮动栅极相邻的擦除栅极。 擦除栅极具有在浮动栅极上延伸的突出端。 悬垂尺寸与浮动栅极和擦除栅极之间的垂直间隔的尺寸之比在1.0和2.5之间，这提高了擦除效率。