公开(公告)号：US07596041B2

公开(公告)日：2009-09-29

申请号：US11905683

申请日：2007-10-03

申请人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara

发明人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara

IPC分类号： G11C7/00

CPC分类号： G06F13/385 ,  G11C5/14 ,  G11C7/24

摘要： The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an emergency stop is received from an information processor of a host during a read/write data transfer process, a control circuit immediately stops the transfer process and notifies the information processor of end of the read data transfer. At this time, the end of read data transfer is notified irrespective of whether the transfer is finished normally or abnormally. Even when a read data transfer request is received again from the information processor after notifying the information processor of the end of read data transfer, without transferring data, a controller notifies the information processor of an untransferable state of read data.

摘要翻译： 本发明旨在通过在数据传送过程中即使基于紧急停止请求来确保数据的保护来大大提高可靠性。 本发明提供一种采用存储卡等形式的数据存储系统。 在读/写数据传送处理期间，当从主机的信息处理器接收到请求紧急停止的紧急停止信号时，控制电路立即停止传送处理，并向信息处理器通知读取的数据传送结束。 此时，无论传输是正常还是异常地完成，都会通知读取数据传输的结束。 即使当在通知信息处理器之后再次从信息处理器接收到读取数据传送的结束而不传送数据时，控制器向信息处理器通知读取数据的不可转移的状态。

公开(公告)号：US07552311B2

公开(公告)日：2009-06-23

申请号：US11711084

申请日：2007-02-27

申请人： Fumio Hara ,  Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya

发明人： Fumio Hara ,  Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0866 ,  G06F2212/2146 ,  G06F2212/6022

摘要： The present invention provides a memory device that can flexibly decide the data to be preread. The memory device according to the present invention includes: a nonvolatile memory; a buffer memory having a higher access speed than the nonvolatile memory; and a control circuit. The control circuit creates a preread data management table that associates a logical address of preread data specified by a preread command inputted from the outside and a buffer memory address for storing the preread data. Moreover, the control circuit reads data specified by the command from the nonvolatile memory and stores it in the buffer memory as preread data. When a logical address specified in a read command inputted from the outside matches a logical address associated by the preread data management table, the control circuit outputs corresponding preread data from the buffer memory.

摘要翻译： 本发明提供一种可以灵活地决定要被预读的数据的存储装置。 根据本发明的存储装置包括：非易失性存储器; 具有比非易失性存储器更高的访问速度的缓冲存储器; 和控制电路。 控制电路创建一个预读数据管理表，其将从外部输入的预读命令指定的预读数据的逻辑地址与用于存储预读数据的缓冲存储器地址相关联。 此外，控制电路从非易失性存储器读取由该命令指定的数据，并将其作为预读数据存储在缓冲存储器中。 当从外部输入的读取命令中指定的逻辑地址与由预读数据管理表相关联的逻辑地址匹配时，控制电路从缓冲存储器输出对应的预读数据。

公开(公告)号：US07475165B2

公开(公告)日：2009-01-06

申请号：US11058254

申请日：2005-02-16

申请人： Kinji Mitani ,  Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara

发明人： Kinji Mitani ,  Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara

IPC分类号： G06F13/10

CPC分类号： G11C17/16 ,  G11C16/20

摘要： Production cost for a semiconductor data storage apparatus is significantly reduced by using the same controller to support an external analog module and an internal analog module. In a data processing system, a controller is provided with switching elements composed of fuses. Switching between the external analog module composed of an external power supply circuit, an external power supply monitor circuit, and a clock generator element and the internal analog module composed of an internal power supply circuit, an internal power supply monitor circuit, and a self-excited oscillator circuit is performed by arbitrarily disconnecting the fuses. For example, when an internal power supply voltage Vdd1 generated by the external power supply monitor circuit is supplied to the controller or the like, the fuse is disconnected. Thus, measures can be taken in accordance with a purpose by, e.g., selecting the external analog module when an interleave operation is used.

摘要翻译： 通过使用相同的控制器来支持外部模拟模块和内部模拟模块，显着减少了半导体数据存储装置的生产成本。 在数据处理系统中，控制器具有由保险丝组成的开关元件。 在由外部电源电路，外部电源监视器电路和时钟发生器元件组成的外部模拟模块之间切换，以及内部电源电路，内部电源监视电路， 激励振荡器电路通过任意断开保险丝来执行。 例如，当将由外部电源监视电路产生的内部电源电压Vdd1提供给控制器等时，熔丝断开。 因此，当使用交错操作时，可以通过例如选择外部模拟模块来根据目的采取措施。

公开(公告)号：US20080137452A1

公开(公告)日：2008-06-12

申请号：US11905683

申请日：2007-10-03

申请人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara

发明人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara

IPC分类号： G11C7/00

CPC分类号： G06F13/385 ,  G11C5/14 ,  G11C7/24

摘要： The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an emergency stop is received from an information processor of a host during a read/write data transfer process, a control circuit immediately stops the transfer process and notifies the information processor of end of the read data transfer. At this time, the end of read data transfer is notified irrespective of whether the transfer is finished normally or abnormally. Even when a read data transfer request is received again from the information processor after notifying the information processor of the end of read data transfer, without transferring data, a controller notifies the information processor of an untransferable state of read data.

摘要翻译： 本发明旨在通过在数据传送过程中即使基于紧急停止请求来确保数据的保护来大大提高可靠性。 本发明提供一种采用存储卡等形式的数据存储系统。 在读/写数据传送处理期间，当从主机的信息处理器接收到请求紧急停止的紧急停止信号时，控制电路立即停止传送处理，并向信息处理器通知读取的数据传送结束。 此时，无论传输是正常还是异常地完成，都会通知读取数据传输的结束。 即使当在通知信息处理器之后再次从信息处理器接收到读取数据传送的结束而不传送数据时，控制器向信息处理器通知读取数据的不可转移的状态。

公开(公告)号：US20070147150A1

公开(公告)日：2007-06-28

申请号：US11711085

申请日：2007-02-27

申请人： Hirofumi Shibuya ,  Fumio Hara ,  Hiroyuki Goto ,  Shigemasa Shiota

发明人： Hirofumi Shibuya ,  Fumio Hara ,  Hiroyuki Goto ,  Shigemasa Shiota

IPC分类号： G11C29/00

CPC分类号： G06F11/1666 ,  G06F11/004 ,  G06F11/20 ,  G06F11/2053 ,  G11C16/04 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/76 ,  G11C2029/0407 ,  G11C2029/0409 ,  G11C2229/723

摘要： It is aimed to detect, notify, and save an abnormal area in semiconductor memory for greatly improving reliability. An inside of semiconductor memories provided for a memory card comprises a user area, a substitution area, an area substitution information storage area, and a management area. An inside of semiconductor memories comprises a user area, a substitution area, and a management area. The user area is a data area a user can use. The substitution area is substituted when an error occurs in the user area. The area substitution information storage area stores area substitution area information. The management area stores substitution information. The information processing section performs substitution on two levels as follows. When detecting an operation indicating a symptom of failure in a semiconductor memory area, the information processing section performs area substitution during an idle state of the memory card. When detecting a faulty operation in an area, the information processing section immediately performs area substitution.

公开(公告)号：US07191308B2

公开(公告)日：2007-03-13

申请号：US10811961

申请日：2004-03-30

申请人： Fumio Hara ,  Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya

发明人： Fumio Hara ,  Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0862 ,  G06F12/0866 ,  G06F2212/2146 ,  G06F2212/6022

摘要： The present invention provides a memory device that can flexibly decide the data to be preread. The memory device according to the present invention includes: a nonvolatile memory; a buffer memory having a higher access speed than the nonvolatile memory; and a control circuit. The control circuit creates a preread data management table that associates a logical address of preread data specified by a preread command inputted from the outside and a buffer memory address for storing the preread data. Moreover, the control circuit reads data specified by the command from the nonvolatile memory and stores it in the buffer memory as preread data. When a logical address specified in a read command inputted from the outside matches a logical address associated by the preread data management table, the control circuit outputs corresponding preread data from the buffer memory.

摘要翻译： 本发明提供一种可以灵活地决定要被预读的数据的存储装置。 根据本发明的存储装置包括：非易失性存储器; 具有比非易失性存储器更高的访问速度的缓冲存储器; 和控制电路。 控制电路创建一个预读数据管理表，其将从外部输入的预读命令指定的预读数据的逻辑地址与用于存储预读数据的缓冲存储器地址相关联。 此外，控制电路从非易失性存储器读取由该命令指定的数据，并将其作为预读数据存储在缓冲存储器中。 当从外部输入的读取命令中指定的逻辑地址与由预读数据管理表相关联的逻辑地址匹配时，控制电路从缓冲存储器输出对应的预读数据。

公开(公告)号：US07137027B2

公开(公告)日：2006-11-14

申请号：US10756292

申请日：2004-01-14

申请人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

发明人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara ,  Kinji Mitani

IPC分类号： G06F11/00

CPC分类号： G11C16/349

摘要： A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.

摘要翻译： 提供允许许多替代存储器块准备好以延长可重写寿命并由此有助于提高信息存储的可靠性的存储器系统。 该存储器系统具有非易失性存储器，该非易失性存储器具有预定物理地址单元中的多个数据块，以及用于响应于来自外部的访问请求来控制该非易失性存储器的控制器。 每个数据块具有用于保存关于每个数据区的重写计数和错误检查信息的区域。 控制器在非易失性存储器中的读取操作中，根据错误检查信息检查受读取区域的任何错误，并且当存在任何错误时，如果重写计数大于预定值，则将替换 与另一个数据块相关的数据块，或者如果不大于数据块，则与错误相关的数据块中的数据正确。

公开(公告)号：US20060239086A1

公开(公告)日：2006-10-26

申请号：US11450435

申请日：2006-06-12

申请人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara

发明人： Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara

IPC分类号： G11C7/00

CPC分类号： G06F13/385 ,  G11C5/14 ,  G11C7/24

摘要： The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an emergency stop is received from an information processor of a host during a read/write data transfer process, a control circuit immediately stops the transfer process and notifies the information processor of end of the read data transfer. At this time, the end of read data transfer is notified irrespective of whether the transfer is finished normally or abnormally. Even when a read data transfer request is received again from the information processor after notifying the information processor of the end of read data transfer, without transferring data, a controller notifies the information processor of an untransferable state of read data.

公开(公告)号：US20050185488A1

公开(公告)日：2005-08-25

申请号：US11058254

申请日：2005-02-16

申请人： Kinji Mitani ,  Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara

发明人： Kinji Mitani ,  Shigemasa Shiota ,  Hiroyuki Goto ,  Hirofumi Shibuya ,  Fumio Hara

IPC分类号： G06K19/07 ,  G06F12/00 ,  G11C7/00 ,  G11C16/20 ,  G11C17/16

CPC分类号： G11C17/16 ,  G11C16/20

摘要： Production cost for a semiconductor data storage apparatus is significantly reduced by using the same controller to support an external analog module and an internal analog module. In a data processing system, a controller is provided with switching elements composed of fuses. Switching between the external analog module composed of an external power supply circuit, an external power supply monitor circuit, and a clock generator element and the internal analog module composed of an internal power supply circuit, an internal power supply monitor circuit, and a self-excited oscillator circuit is performed by arbitrarily disconnecting the fuses. For example, when an internal power supply voltage Vdd1 generated by the external power supply monitor circuit is supplied to the controller or the like, the fuse is disconnected. Thus, measures can be taken in accordance with a purpose by, e.g., selecting the external analog module when an interleave operation is used.

摘要翻译： 通过使用相同的控制器来支持外部模拟模块和内部模拟模块，显着减少了半导体数据存储装置的生产成本。 在数据处理系统中，控制器具有由保险丝组成的开关元件。 在由外部电源电路，外部电源监视器电路和时钟发生器元件组成的外部模拟模块之间切换，以及内部电源电路，内部电源监视电路， 激励振荡器电路通过任意断开保险丝来执行。 例如，当由外部电源监视电路产生的内部电源电压Vdd1被提供给控制器等时，熔断器被断开。 因此，当使用交错操作时，可以通过例如选择外部模拟模块来根据目的采取措施。