Image processing apparatus and image processing method
    44.
    发明授权
    Image processing apparatus and image processing method 失效
    图像处理装置和图像处理方法

    公开(公告)号:US08259991B2

    公开(公告)日:2012-09-04

    申请号:US11812343

    申请日:2007-06-18

    CPC classification number: H04N1/32149 H04N1/32288

    Abstract: An image processing apparatus embedding information in an image by combining multiple predetermined patterns with the image is disclosed that includes a level determination part configured to determine at least one of the levels of conditions to be added regarding the disposition of the predetermined patterns, to which at least one of the levels the information to be embedded belongs; and a pattern combining part configured to combine the predetermined patterns with the image in accordance with the condition corresponding to the information to be embedded at the determined at least one of the levels. If the information to be embedded belongs to two or more of the levels, the pattern combining part combines the predetermined patterns so that the conditions corresponding to the information to be embedded are satisfied at the two or more of the levels.

    Abstract translation: 公开了一种图像处理装置,其通过将多个预定图案与图像组合来将信息嵌入到图像中,该图像处理装置包括:电平确定部件,被配置为确定关于预定图案的配置的待添加条件的水平中的至少一个, 待嵌入信息的最低级别之一属于; 以及图案组合部分,被配置为根据与要在所确定的至少一个级别嵌入的信息相对应的条件将预定图案与图像组合。 如果要嵌入的信息属于两个或更多个级别,则模式组合部分组合预定模式,使得在两个或更多个级别满足与要嵌入的信息相对应的条件。

    Apparatus, system, and method for image processing
    45.
    发明授权
    Apparatus, system, and method for image processing 有权
    用于图像处理的装置,系统和方法

    公开(公告)号:US08208179B2

    公开(公告)日:2012-06-26

    申请号:US12320504

    申请日:2009-01-28

    Abstract: An image processing apparatus includes an image information acquisition device, an embedment information acquisition device, an embedment mode information acquisition device, an embeddability determination device, and an embeddability information output device. The image information acquisition device acquires image information on a target image into which supplemental information is to be embedded. The embedment information acquisition device acquires embedment information on the supplemental information. The embedment mode information acquisition device acquires embedment mode information on an embedment mode in which the supplemental information is embedded in the image information. The embeddability determination device determines embeddability of the supplemental information into the image information based on the embedment mode information, the embedment information, and the image information. The embeddability information output device outputs determination-result information on a determination result of the embeddability determined by the embeddability determination device.

    Abstract translation: 图像处理装置包括图像信息获取装置,嵌入信息获取装置,嵌入模式信息获取装置,嵌入性判定装置和可嵌入信息输出装置。 图像信息获取装置获取关于要嵌入补充信息的目标图像的图像信息。 嵌入信息获取装置获取关于补充信息的嵌入信息。 嵌入模式信息获取装置获取嵌入模式信息,该嵌入模式信息是将补充信息嵌入在图像信息中的嵌入模式。 可嵌入性确定装置基于嵌入模式信息,嵌入信息和图像信息,将补充信息的嵌入性确定为图像信息。 嵌入性信息输出装置输出关于由嵌入性判定装置确定的嵌入性的确定结果的确定结果信息。

    Method, program, and apparatus for detecting a copy-prohibited document and prohibiting a reproduction of the detected copy prohibited document
    47.
    发明授权
    Method, program, and apparatus for detecting a copy-prohibited document and prohibiting a reproduction of the detected copy prohibited document 失效
    用于检测禁止复印件的文件的方法,程序和装置,并禁止复制所检测到的禁止拷贝的文件

    公开(公告)号:US08009305B2

    公开(公告)日:2011-08-30

    申请号:US10922924

    申请日:2004-08-23

    CPC classification number: H04N1/00846 H04N1/00867 H04N1/00875

    Abstract: An image processing apparatus includes a first memory, a data detector, a second memory, a third memory, and a determiner. The first memory stores a reference pattern including a plurality of reference basic units, each of which represents specific minimal information, is superposed on input image data, and represents specific entire information. The data detector detects a basic unit in the input image data based on the reference basic unit included in the reference pattern stored in the first memory. The second memory accumulates a number of basic units detected by the data detector. The third memory stores a predetermined value. The determiner determines whether the number of basic units detected by the data detector and stored in the second memory is equal to the predetermined value stored in the third memory.

    Abstract translation: 图像处理装置包括第一存储器,数据检测器,第二存储器,第三存储器和确定器。 第一存储器存储包括多个参考基本单元的参考图案,每个基准单元表示特定的最小信息,叠加在输入图像数据上,并且表示特定的整个信息。 数据检测器基于存储在第一存储器中的参考图形中包括的参考基本单元检测输入图像数据中的基本单元。 第二存储器累积由数据检测器检测的多个基本单元。 第三存储器存储预定值。 确定器确定由数据检测器检测并存储在第二存储器中的基本单元的数量是否等于存储在第三存储器中的预定值。

    IC containing matrices of plural type operation units with configurable routing wiring group and plural delay operation units bridging two wiring groups
    49.
    发明授权
    IC containing matrices of plural type operation units with configurable routing wiring group and plural delay operation units bridging two wiring groups 有权
    具有可配置路由布线组的多种类型操作单元的IC包含矩阵,以及桥接两个布线组的多个延迟操作单元

    公开(公告)号:US07577821B2

    公开(公告)日:2009-08-18

    申请号:US11670302

    申请日:2007-02-01

    CPC classification number: G06F17/5045 G06F15/7867

    Abstract: An integrated circuit device comprising a data processing block including a first matrix and a second matrix is disclosed. The first matrix and the second matrix respectively include a plurality of types of operation units and a wiring group for connecting the plurality of types of operation units, a configuration of data flow with the plurality of types of operation units being changeable by changing a route of the wiring group for data supplying to the plurality of types of operation units. One of the plurality of types of operation units is a delay type operation unit that include a data path suited to processing for delaying a transfer time of data. The wiring group of the first matrix and the wiring group of the second matrix are separated, and the integrated circuit device further comprises a plurality of the delay type operation units that are arranged along boundary of the first matrix and the second matrix for connecting the wiring group of the first matrix and the wiring group of the second matrix via data paths included in the plurality of the delay type operation units.

    Abstract translation: 公开了一种包括包括第一矩阵和第二矩阵的数据处理块的集成电路装置。 第一矩阵和第二矩阵分别包括多种类型的操作单元和用于连接多种类型的操作单元的布线组,可以通过改变多种类型的操作单元的路线来改变多种类型的操作单元的数据流的配置 用于向多种类型的操作单元提供数据的接线组。 多种类型的操作单元之一是延迟型操作单元,其包括适于延迟数据传送时间的处理的数据路径。 分离第一矩阵的布线组和第二矩阵的布线组,并且集成电路装置还包括沿着第一矩阵和第二矩阵的边界布置的多个延迟型操作单元,用于连接布线 通过包括在多个延迟型操作单元中的数据路径,第二矩阵的布线组和第二矩阵的布线组。

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