公开(公告)号：US20140145772A1

公开(公告)日：2014-05-29

申请号：US14089780

申请日：2013-11-26

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund

IPC: G11C11/41

CPC classification number: G11C11/41 ,  G11C7/1006 ,  G11C7/1009 ,  H03K3/0372

Abstract: In accordance with an embodiment, a description is given of a storage circuit including an input stage configured to provide a value to be stored, a storage stage configured to store the value to be stored, an output stage configured to output a value stored by the storage circuit, and a control circuit, wherein the control circuit is configured to receive a signal from the output stage, which signal indicates the charge state of the output stage, and, if the charge state of the output stage is equal to a predefined precharge state, to output an activation signal to the storage stage, and wherein the storage stage is configured to store the value to be stored, provided by the input stage, in reaction to the activation signal.

Abstract translation: 根据实施例，给出了包括被配置为提供要存储的值的输入级的存储电路，被配置为存储要存储的值的存储级，输出级，其被配置为输出存储的值 存储电路和控制电路，其中所述控制电路被配置为从所述输出级接收信号，所述信号指示所述输出级的充电状态，并且如果所述输出级的充电状态等于预定义的预充电 状态，以将激活信号输出到所述存储级，并且其中所述存储级被配置为存储由所述输入级提供的要存储的值，以响应于所述激活信号。

公开(公告)号：US10607033B2

公开(公告)日：2020-03-31

申请号：US15883120

申请日：2018-01-30

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Berndt Gammel

IPC: G06F21/75 ,  G06F21/73 ,  G06F21/72 ,  H04L9/32 ,  G11C7/10 ,  G11C7/24 ,  H04L9/08 ,  G09C1/00 ,  G11C11/412 ,  G11C11/419 ,  H03K19/003

Abstract: According to one embodiment, a physical uncloneable function circuit for providing a protected output bit is described including at least one physical uncloneable function circuit element configured to output a bit of a physical uncloneable function value, a physical uncloneable function bit output terminal and a coupling circuit connected between the physical uncloneable function circuit element and the physical uncloneable function bit output terminal configured to receive a control signal, supply the bit to the physical uncloneable function bit output terminal for a first state of the control signal and supply the complement of the bit to the physical uncloneable function bit output terminal for a second state of the control signal.

公开(公告)号：US20190333868A1

公开(公告)日：2019-10-31

申请号：US16510371

申请日：2019-07-12

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Hans Friedinger

IPC: H01L23/552 ,  H03K3/037 ,  H01L23/00 ,  G06F21/75

Abstract: A chip having a substrate region having a substrate contact, an RS latch having two complementary nodes representing a storage state of the RS latch, a control circuit having a control input and configured to connect one of the complementary nodes to a supply potential depending on a potential at the control input, wherein the control input is connected to the substrate contact, and an output circuit connected to an output of the RS latch and configured to trigger an alarm depending on the storage state of the RS latch.

公开(公告)号：US10418999B2

公开(公告)日：2019-09-17

申请号：US15701478

申请日：2017-09-12

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund

IPC: H03K19/177 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/173 ,  H03K19/20

Abstract: According to an embodiment, a programmable logic circuit is described comprising a first data bit input to receive a first data bit a and a second data bit input to receive a second data bit b, a first program bit input to receive a first program bit p1, a second program bit input to receive a second program bit p2, a third program bit input to receive a third program bit p3 and a fourth program bit to receive a fourth program bit p4 and an output configured to output ( ( ( a ⋀ b ) ⋁ ( p 1 ⋀ a ) ⋁ ( p 2 ⋀ b ) ) _ ⋀ ( p 3 ⋁ b ⋁ a ) ) ⋁ ( a ⋀ b ⋀ p 4 ) _ .

公开(公告)号：US10418996B2

公开(公告)日：2019-09-17

申请号：US15718033

申请日：2017-09-28

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Molka Ben Romdhane ,  Berndt Gammel

IPC: H03K19/007 ,  H03K3/3562

Abstract: According to an embodiment, a circuit is described comprising a plurality of flip-flops, a control circuit configured to provide a control signal to each flip-flop of the plurality of flip-flops and an integrity checking circuit connected to the control circuit and to the plurality of flip-flops configured to check whether the flip-flops receive the control signal as provided by the control circuit.

公开(公告)号：US10410980B2

公开(公告)日：2019-09-10

申请号：US15841379

申请日：2017-12-14

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Mayk Roehrich

IPC: H01L23/00 ,  H01L27/02 ,  H01L27/092 ,  G06F21/72 ,  H01L21/8238 ,  G06F21/00 ,  H01L27/118

Abstract: According to one embodiment, a semiconductor chip is described including a semiconductor chip body and a semiconductor chip circuit on the body and including a first circuit path coupled to a first and a second node and including at least two gate-insulator-semiconductor structures and a second circuit path coupled to the first and the second node and including at least two gate-insulator-semiconductor structures. The first and the second circuit path are connected to set the first and the second node to complementary logic states. In each of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured as field effect transistor. In at least one of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured to connect the circuit path to the semiconductor body.

公开(公告)号：US10395063B2

公开(公告)日：2019-08-27

申请号：US15272458

申请日：2016-09-22

Applicant: Infineon Technologies AG

Inventor： Franz Klug ,  Thomas Kuenemund

IPC: H04L29/06 ,  G06F21/71 ,  G06F7/00 ,  G06F21/55 ,  G06F21/62 ,  H04L9/00 ,  H03K5/1536 ,  H03K5/22

Abstract: A zero detection circuit includes a chain of masked OR circuits. Each masked OR circuit includes data inputs. Each data input is configured to receive a respective data input bit. Each masked OR circuit further includes an input mask input to receive one or more input masking bits, an output mask input to receive an output masking bit and a data output. The zero detection circuit is configured to output a bit equal to an OR combination, masked with the output masking bit, of the data input bits, each demasked with an input masking bit of the one or more input masking bits. One of the inputs of each masked OR circuit except the first masked OR circuit of the chain of masked OR circuits is coupled to the data output of the masked OR circuit preceding the masked OR circuit in the chain of masked OR circuits.

公开(公告)号：US10347630B2

公开(公告)日：2019-07-09

申请号：US15135610

申请日：2016-04-22

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund

IPC: H01L27/092 ,  H01L23/528 ,  H01L23/00 ,  H03K19/003 ,  H03K19/0948 ,  H03K19/21

Abstract: According to one embodiment, a chip has a circuit with at least one p channel field effect transistor (FET); at least one n channel FET; a first and a second power supply terminal; wherein the n channel FET, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the p channel FET; and the p channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the n channel FET; wherein the logic state of the gate of the p channel FET and of the n channel FET can only be changed by at least one of the first and second supply voltage to the circuit; and a connection coupled to the gate of the p channel FET or the n channel FET and a further component of the semiconductor chip.

公开(公告)号：US10249219B2

公开(公告)日：2019-04-02

申请号：US14882542

申请日：2015-10-14

Applicant: Infineon Technologies AG

Inventor： Wieland Fischer ,  Thomas Kuenemund ,  Bernd Meyer

IPC: G09C1/00

Abstract: According to one embodiment, a processing circuit is described including a first input path and a second input path, a processing element configured to receive a first input bit and a second input bit via the first input path and the second input path and configured to perform a logic operation which is commutative with respect to the first input bit and the second input bit and a sorter configured to distribute the first input bit and the second input bit to the first input path and the second input path according to a predetermined sorting rule.

公开(公告)号：US20180174985A1

公开(公告)日：2018-06-21

申请号：US15841379

申请日：2017-12-14

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Mayk Roehrich

IPC: H01L23/00 ,  H01L27/092 ,  H01L27/02

CPC classification number: H01L23/576 ,  G06F21/00 ,  G06F21/72 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11838

Abstract: According to one embodiment, a semiconductor chip is described including a semiconductor chip body and a semiconductor chip circuit on the body and including a first circuit path coupled to a first and a second node and including at least two gate-insulator-semiconductor structures and a second circuit path coupled to the first and the second node and including at least two gate-insulator-semiconductor structures. The first and the second circuit path are connected to set the first and the second node to complementary logic states. In each of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured as field effect transistor. In at least one of the first and the second circuit path, at least one of the gate-insulator-semiconductor structures is configured to connect the circuit path to the semiconductor body.