公开(公告)号：US20190265777A1

公开(公告)日：2019-08-29

申请号：US16288580

申请日：2019-02-28

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Edward T. Grochowski ,  Daehyun Kim ,  Yuxin Bai ,  Sheng Li ,  Naveen K. Mellempudi ,  Dhiraj D. Kalamkar

IPC: G06F1/3287 ,  G06F9/50 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/329 ,  G06F1/3296 ,  G06F1/324

Abstract: In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

公开(公告)号：US10261904B2

公开(公告)日：2019-04-16

申请号：US15835384

申请日：2017-12-07

Applicant: Intel Corporation

Inventor： Chunhui Zhang ,  George Z. Chrysos ,  Edward T. Grochowski ,  Ramacharan Sundararaman ,  Chung-Lun Chan ,  Federico Ardanaz

IPC: G06F9/38 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0842

Abstract: Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.

公开(公告)号：US10234930B2

公开(公告)日：2019-03-19

申请号：US14621709

申请日：2015-02-13

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Edward T. Grochowski ,  Daehyun Kim ,  Yuxin Bai ,  Sheng Li ,  Naveen K. Mellempudi ,  Dhiraj D. Kalamkar

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/50

Abstract: In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.