公开(公告)号：US10146286B2

公开(公告)日：2018-12-04

申请号：US14995263

申请日：2016-01-14

申请人： Intel Corporation

发明人： Victor W. Lee ,  Yuxin Bai

IPC分类号： G06F1/00 ,  G06F1/28 ,  G06N99/00 ,  G06F1/32 ,  G06F1/30

摘要： In one embodiment, A processor includes a logic to receive performance monitoring information from at least some of a plurality of cores and determine, according to a power management model, a performance state for one or more of the plurality of cores based on the performance monitoring information, and a second logic to receive the performance monitoring information and dynamically update the power management model according to a reinforcement learning process. Other embodiments are described and claimed.

公开(公告)号：US20170205863A1

公开(公告)日：2017-07-20

申请号：US14995263

申请日：2016-01-14

申请人： Intel Corporation

发明人： Victor W. Lee ,  Yuxin Bai

IPC分类号： G06F1/28 ,  G06N99/00

CPC分类号： G06F1/28 ,  G06F1/30 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06N99/005 ,  Y02D10/124 ,  Y02D10/126 ,  Y02D10/172

摘要： In one embodiment, A processor includes a logic to receive performance monitoring information from at least some of a plurality of cores and determine, according to a power management model, a performance state for one or more of the plurality of cores based on the performance monitoring information, and a second logic to receive the performance monitoring information and dynamically update the power management model according to a reinforcement learning process. Other embodiments are described and claimed.

公开(公告)号：US10775873B2

公开(公告)日：2020-09-15

申请号：US16288580

申请日：2019-02-28

申请人： Intel Corporation

发明人： Victor W. Lee ,  Edward T. Grochowski ,  Daehyun Kim ,  Yuxin Bai ,  Sheng Li ,  Naveen K. Mellempudi ,  Dhiraj D. Kalamkar

IPC分类号： G06F1/00 ,  G06F1/3287 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/50

摘要： In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

公开(公告)号：US20190265777A1

公开(公告)日：2019-08-29

申请号：US16288580

申请日：2019-02-28

申请人： Intel Corporation

发明人： Victor W. Lee ,  Edward T. Grochowski ,  Daehyun Kim ,  Yuxin Bai ,  Sheng Li ,  Naveen K. Mellempudi ,  Dhiraj D. Kalamkar

IPC分类号： G06F1/3287 ,  G06F9/50 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/329 ,  G06F1/3296 ,  G06F1/324

摘要： In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

公开(公告)号：US10234930B2

公开(公告)日：2019-03-19

申请号：US14621709

申请日：2015-02-13

申请人： Intel Corporation

发明人： Victor W. Lee ,  Edward T. Grochowski ,  Daehyun Kim ,  Yuxin Bai ,  Sheng Li ,  Naveen K. Mellempudi ,  Dhiraj D. Kalamkar

IPC分类号： G06F1/32 ,  G06F1/3287 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/50

摘要： In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

公开(公告)号：US09910481B2

公开(公告)日：2018-03-06

申请号：US14621731

申请日：2015-02-13

申请人： Intel Corporation

发明人： Victor W. Lee ,  Daehyun Kim ,  Yuxin Bai ,  Shihao Ji ,  Sheng Li ,  Dhiraj D. Kalamkar ,  Naveen K. Mellempudi

IPC分类号： G06F1/32 ,  G06F9/50

CPC分类号： G06F1/324 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/5088 ,  G06F9/5094 ,  Y02D10/124 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/22 ,  Y02D10/32

摘要： In an embodiment, a processor a plurality of cores to independently execute instructions, the cores including a plurality of counters to store performance information, and a power controller coupled to the plurality of cores, the power controller having a logic to receive performance information from at least some of the plurality of counters, determine a number of cores to be active and a performance state for the number of cores for a next operation interval, based at least in part on the performance information and model information, and cause the number of cores to be active during the next operation interval, the performance information associated with execution of a workload on one or more of the plurality of cores. Other embodiments are described and claimed.