公开(公告)号：US09946676B2

公开(公告)日：2018-04-17

申请号：US14669975

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Zuoguo Wu ,  Venkatraman Iyer ,  Gerald S. Pasdast ,  Mark S. Birrittella ,  Ishwar Agarwal ,  Lip Khoon Teh ,  Su Wei Lim ,  Anoop Kumar Upadhyay

IPC: G06F17/50 ,  G06F13/40 ,  G06F13/36

CPC classification number: G06F13/4022 ,  G06F13/36 ,  G06F13/4068

Abstract: A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k≠h, so that ┌k/n┐ hard IP blocks provide h=n*p available hard IP data lanes. In that case, h−k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.

公开(公告)号：US20180089115A1

公开(公告)日：2018-03-29

申请号：US15280730

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Mark A. Schmisseur ,  Raj K. Ramanujan ,  Filip Schmole ,  David M. Lee ,  Ishwar Agarwal ,  David J. Harriman

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/02 ,  G06F12/128

CPC classification number: G06F13/1694 ,  G06F12/0246 ,  G06F12/12 ,  G06F13/4282

Abstract: Aspects of the disclosure are directed to systems, methods, and devices that include an application processor. The application processor includes an interface logic to interface with a communication module using a bidirectional interconnect link compliant with a peripheral component interconnect express (PCIe) protocol. The interface logic to receive a data packet from across the link, the data packet comprises a header and data payload; determine a hint bit set in the header of the data packet; determine a steering tag value in the data packet header based on the hint bit set; and transmit the data payload to non-volatile memory based on the steering tag set in the header.