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    Efficient key derivation for end-to-end network security with traffic visibility
    42.
    发明授权
    Efficient key derivation for end-to-end network security with traffic visibility 有权
    针对具有流量可见性的端到端网络安全性的高效密钥导出

    公开(公告)号：US08903084B2

    公开(公告)日：2014-12-02

    申请号：US13916027

    申请日：2013-06-12

    Applicant: Intel Corporation

    Inventor： Men Long ,  Jesse Walker ,  Karanvir S. Grewal

    IPC: H04L9/00 ,  H04L9/08 ,  G06F7/04 ,  G06F21/00 ,  H04L29/06 ,  H04L9/06

    CPC classification number: H04L9/0866 ,  H04L9/0631 ,  H04L63/0428 ,  H04L63/06 ,  H04L2209/125

    Abstract: Both end-to-end security and traffic visibility may be achieved by a system using a controller that derives a cryptographic key that is different for each client based on a derivation key and a client identifier that is conveyed in each data packet. The controller distributes the derivation key to information technology monitoring devices and a server to provide traffic visibility. For large key sizes, the key may be derived using a derivation formula as follows: client_key_MSB=AES128(base_key_1,client_ID),  (1) client_key_LSB=AES128(base_key_2,client_ID+pad),and  (2) client_key=client_key_MSB∥client_key_LSB, where (1) and (2) are executed in parallel. The client key and a client identifier may be used so that end-to-end security may be achieved.

    Abstract translation: 端到端安全性和流量可见性可以由使用控制器的系统来实现，所述控制器基于在每个数据分组中传送的导出密钥和客户端标识符来导出每个客户端不同的密码密钥。 控制器将派生密钥分发到信息技术监控设备和服务器，以提供流量可视性。 对于较大的密钥大小，可以使用如下的推导公式来导出密钥：client_key_MSB = AES128（base_key_1，client_ID），（1）client_key_LSB = AES128（base_key_2，client_ID + pad）和（2）cli​​ent_key =client_key_MSB‖client_key_LSB， 其中（1）和（2）并行执行。 可以使用客户端密钥和客户端标识符，以便可以实现端到端的安全性。

    TECHNOLOGIES FOR EXECUTE ONLY TRANSACTIONAL MEMORY
    43.
    发明申请
    TECHNOLOGIES FOR EXECUTE ONLY TRANSACTIONAL MEMORY 有权

    公开(公告)号：US20220382684A1

    公开(公告)日：2022-12-01

    申请号：US17819418

    申请日：2022-08-12

    Applicant: Intel Corporation

    Inventor： David M. Durham ,  Michael LeMay ,  Men Long

    IPC: G06F12/1027 ,  G06F12/14 ,  G06F9/30

    Abstract: Technologies for execute only transactional memory include a computing device with a processor and a memory. The processor includes an instruction translation lookaside buffer (iTLB) and a data translation lookaside buffer (dTLB). In response to a page miss, the processor determines whether a page physical address is within an execute only transactional (XOT) range of the memory. If within the XOT range, the processor may populate the iTLB with the page physical address and prevent the dTLB from being populated with the page physical address. In response to an asynchronous change of control flow such as an interrupt, the processor determines whether a last iTLB translation is within the XOT range. If within the XOT range, the processor clears or otherwise secures the processor register state. The processor ensures that an XOT range starts execution at an authorized entry point. Other embodiments are described and claimed.

    Security plugin for a system-on-a-chip platform
    44.
    发明授权
    Security plugin for a system-on-a-chip platform 有权

    公开(公告)号：US10726162B2

    公开(公告)日：2020-07-28

    申请号：US14577812

    申请日：2014-12-19

    Applicant: Intel Corporation

    Inventor： Manoj R Sastry ,  Alpa Narendra Trivedi ,  Men Long

    IPC: G06F21/72 ,  G09C1/00 ,  G06F21/85 ,  H04L9/06 ,  H04L9/08

    Abstract: Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.

    MEMORY SCANNING METHODS AND APPARATUS
    45.
    发明申请
    MEMORY SCANNING METHODS AND APPARATUS 审中-公开

    公开(公告)号：US20200050764A1

    公开(公告)日：2020-02-13

    申请号：US16657669

    申请日：2019-10-18

    Applicant: Intel Corporation

    Inventor： Michael LeMay ,  David M. Durham ,  Men Long

    IPC: G06F21/56 ,  G06F12/0802 ,  G06F12/1009

    Abstract: Memory scanning methods and apparatus are disclosed. An example apparatus includes an address identifier to, when an entry of a paging structure has been accessed, determine a first address corresponding to a page of physical memory when the entry of the paging structure maps to the page of the physical memory; and a scanner to: scan a threshold amount of memory beginning at a physical memory address corresponding to the first address; and determine whether the threshold amount of memory includes a pattern indicative of malware.

    Technologies for execute only transactional memory
    46.
    发明授权
    Technologies for execute only transactional memory 有权

    公开(公告)号：US10558582B2

    公开(公告)日：2020-02-11

    申请号：US14974972

    申请日：2015-12-18

    Applicant: Intel Corporation

    Inventor： David M. Durham ,  Michael Lemay ,  Men Long

    IPC: G06F12/00 ,  G06F12/1027 ,  G06F9/30 ,  G06F12/14

    Abstract: Technologies for execute only transactional memory include a computing device with a processor and a memory. The processor includes an instruction translation lookaside buffer (iTLB) and a data translation lookaside buffer (dTLB). In response to a page miss, the processor determines whether a page physical address is within an execute only transactional (XOT) range of the memory. If within the XOT range, the processor may populate the iTLB with the page physical address and prevent the dTLB from being populated with the page physical address. In response to an asynchronous change of control flow such as an interrupt, the processor determines whether a last iTLB translation is within the XOT range. If within the XOT range, the processor clears or otherwise secures the processor register state. The processor ensures that an XOT range starts execution at an authorized entry point. Other embodiments are described and claimed.

    EFFICIENT SHARING OF HARDWARE ENCRYPTION PIPELINE FOR MULTIPLE SECURITY SOLUTIONS
    50.
    发明申请
    EFFICIENT SHARING OF HARDWARE ENCRYPTION PIPELINE FOR MULTIPLE SECURITY SOLUTIONS 有权
    用于多种安全解决方案的硬件加密管道的高效共享

    公开(公告)号：US20170063532A1

    公开(公告)日：2017-03-02

    申请号：US14753987

    申请日：2015-06-29

    Applicant: Intel Corporation

    Inventor： Binata Bhattacharyya ,  Siddhartha Chhabra ,  Evgeny Zhyvov ,  Eugene M. Kishinevsky ,  Men Long

    IPC: H04L9/06 ,  G06F21/76 ,  G06F21/72

    CPC classification number: H04L9/0637 ,  G06F21/57 ,  G06F21/72 ,  G06F21/76 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/125

    Abstract: A processing or memory device may include a first encryption pipeline to encrypt and decrypt data with a first encryption mode and a second encryption pipeline to encrypt and decrypt data with a second encryption mode, wherein the first encryption pipeline and the second encryption pipeline share a single, shared pipeline for a majority of encryption and decryption operations performed by the first encryption pipeline and by the second encryption pipeline. A controller (and/or other logic) may direct selection of encrypted (or decrypted) data from the first and second encryption pipelines responsive to a region of memory to which a physical address of a memory request is directed. The result of the selection may result in bypassing encryption/decryption or encrypting/decrypting the data according to the first encryption mode or the second encryption mode. More than two encryption modes are envisioned.

    Abstract translation: 处理或存储设备可以包括用第一加密模式加密和解密数据的第一加密流水线和用第二加密模式对数据进行加密和解密的第二加密流水线，其中第一加密流水线和第二加密流水线共享一个 ，用于由第一加密流水线和第二加密流水线执行的大多数加密和解密操作的共享流水线。 响应于存储器请求的物理地址所针对的存储器区域，控制器（和/或其他逻辑）可以直接从第一和第二加密流水线中选择加密（或解密的）数据。 选择的结果可能导致绕过加密/解密或者根据第一加密模式或第二加密模式对数据进行加密/解密。 设想了两种以上的加密模式。

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