公开(公告)号：US20170075822A1

公开(公告)日：2017-03-16

申请号：US15358976

申请日：2016-11-22

Applicant: INTEL CORPORATION

Inventor： Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Men Long ,  Edgar Borrayo ,  Alpa T. Narendra Trivedi ,  Carlos Ornelas

IPC: G06F12/14 ,  G06F9/54 ,  G06F21/72

CPC classification number: G06F12/1408 ,  G06F9/546 ,  G06F13/16 ,  G06F13/1605 ,  G06F21/72 ,  G06F2212/1052 ,  Y02D10/14

Abstract: Memory encryption engine (MEE) integration technologies are described. A MEE system may include a MEE interface and a MEE core. The MEE interface may receive a data from an arbiter, where the data is selected by the arbiter from data at memory link queues. The MEE interface may adjust a timing rate to send the data to match a timing of a MEE core. The MEE core may be coupled to the MEE interface and may receive the data from the MEE interface.

Abstract translation: 描述内存加密引擎（MEE）集成技术。 MEE系统可以包括MEE接口和MEE核。 MEE接口可以从仲裁器接收数据，其中数据由仲裁器从存储器链路队列的数据中选择。 MEE接口可以调整定时速率以发送数据以匹配MEE核的定时。 MEE核可以耦合到MEE接口并且可以从MEE接口接收数据。

公开(公告)号：US09980168B2

公开(公告)日：2018-05-22

申请号：US14750597

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： David Arditti Ilitzky ,  Thomas A. Tetzlaff ,  Edgar Borrayo ,  Stefano Pellerano

IPC: G08C17/00 ,  H04W24/10 ,  H04W52/02 ,  H04B1/06

CPC classification number: H04W24/10 ,  H04B1/06 ,  H04W52/02 ,  Y02D70/00 ,  Y02D70/1222 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/162 ,  Y02D70/26 ,  Y02D70/40

Abstract: This application discusses apparatus and methods of saving power using a quadrature receiver by enabling a single string reception mode of the quadrature receiver. In an example, a receiver for receiving communication information can include an analog front end configured to receive a modulated, information-carrying radio frequency signal at a first frequency band and to provide a digital representation of the modulated, information-carrying radio frequency signal at a second frequency band, a digital front end configured to receive the digital representation at the second frequency and to provide the communication information, for example, to a baseband processor. In a first processing mode of the receiver, the analog front end can provide either one of in-phase symbol information of the modulated, information-carrying radio frequency signal or quadrature symbol information of the modulated, information-carrying radio frequency signal at the second frequency band.

公开(公告)号：US09910793B2

公开(公告)日：2018-03-06

申请号：US15358976

申请日：2016-11-22

Applicant: INTEL CORPORATION

Inventor： Siddhartha Chhabra ,  Uday R. Savagaonkar ,  Men Long ,  Edgar Borrayo ,  Alpa T. Narendra Trivedi ,  Carlos Ornelas

IPC: G06F21/00 ,  G06F12/14 ,  G06F9/54 ,  G06F13/16 ,  G06F21/72

CPC classification number: G06F12/1408 ,  G06F9/546 ,  G06F13/16 ,  G06F13/1605 ,  G06F21/72 ,  G06F2212/1052 ,  Y02D10/14

Abstract: Memory encryption engine (MEE) integration technologies are described. A MEE system may include a MEE interface and a MEE core. The MEE interface may receive a data from an arbiter, where the data is selected by the arbiter from data at memory link queues. The MEE interface may adjust a timing rate to send the data to match a timing of a MEE core. The MEE core may be coupled to the MEE interface and may receive the data from the MEE interface.

公开(公告)号：US09442864B2

公开(公告)日：2016-09-13

申请号：US14142117

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Uday R. Savagaonkar ,  Siddhartha Chhabra ,  Men Long ,  Alpa T. Narendra Trivedi ,  Carlos Ornelas ,  Edgar Borrayo ,  Ramadass Nagarajan ,  Stanley S. Kulick

IPC: G06F12/14 ,  G06F21/74

CPC classification number: G06F12/1408 ,  G06F12/1441 ,  G06F21/74 ,  G06F2212/1052

Abstract: A processor is described that includes one or more processing cores. The processor includes a memory controller to interface with a system memory having a protected region and a non protected region. The processor includes a protection engine to protect against active and passive attacks. The processor includes an encryption/decryption engine to protect against passive attacks. The protection engine includes bridge circuitry coupled between the memory controller and the one or more processing cores. The bridge circuitry is also coupled to the protection engine and the encryption/decryption engine. The bridge circuitry is to route first requests directed to the protected region to the protection engine and to route second requests directed to the non protected region to the encryption/decryption engine.

Abstract translation: 描述了包括一个或多个处理核心的处理器。 处理器包括与具有受保护区域和非保护区域的系统存储器接口的存储器控​​制器。 该处理器包括保护引擎，以防止主动和被动攻击。 该处理器包括一个加密/解密引擎，以防止被动攻击。 保护引擎包括耦合在存储器控制器和一个或多个处理核心之间的桥接电路。 桥接电路还耦合到保护引擎和加密/解密引擎。 桥接电路是将定向到保护区域的第一请求路由到保护引擎，并将定向到非保护区域的第二请求路由到加密/解密引擎。