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    Techniques for secure authentication
    41.
    发明授权
    Techniques for secure authentication 有权

    公开(公告)号：US10326596B2

    公开(公告)日：2019-06-18

    申请号：US15283315

    申请日：2016-10-01

    Applicant: INTEL CORPORATION

    Inventor： Vikram Suresh ,  Sudhir Satpathy ,  Sanu Mathew

    IPC: H04L9/00 ,  H04L9/32 ,  H04L9/06 ,  G06F7/72 ,  G09C1/00 ,  H04L9/28

    Abstract: Various embodiments are generally directed to techniques for secure message authentication and digital signatures, such as with a cipher-based hash function, for instance. Some embodiments are particularly directed to a secure authentication system that implements various aspects of the cipher-based hash function in dedicated hardware or circuitry. In various embodiments, the secure authentication system may implement one or more elements of the Whirlpool hash function in dedicated hardware. For instance, the compute-intensive substitute byte and mix rows blocks of the block cipher in the Whirlpool hash function may be implemented in dedicated hardware or circuitry using a combination of Galois Field arithmetic and fused scale/reduce circuits. In some embodiments, the microarchitecture of the secure authentication system may be implemented with delayed add key to limit the memory requirement to three sequential registers.

    ERROR DETECTION IN CRYPTOGRAPHIC SUBSTITUTION BOX OPERATIONS
    42.
    发明公开
    ERROR DETECTION IN CRYPTOGRAPHIC SUBSTITUTION BOX OPERATIONS 审中-公开

    公开(公告)号：US20240333472A1

    公开(公告)日：2024-10-03

    申请号：US18194270

    申请日：2023-03-31

    Applicant: Intel Corporation

    Inventor： Raghavan Kumar ,  Sanu Mathew ,  Avinash V. Varna ,  Kirk S. YAP

    IPC: H04L9/06

    CPC classification number: H04L9/0631 ,  H04L9/0637

    Abstract: An apparatus of an aspect includes a substitution box (S-box) circuitry. The S-box circuitry includes multiplicative inverse circuitry. The multiplicative inverse circuitry is to receive an 8-bit input in Galois field and is to generate a corresponding 8-bit output in Galois field. The 8-bit output is to be a multiplicative inverse of the 8-bit input as long as there has been no error in the generation of the 8-bit output. The apparatus also includes error detection circuitry to receive the 8-bit input and that is coupled with the S-box circuitry to receive the 8-bit output. The error detection circuitry to detect whether an error has occurred in the generation of the 8-bit output based at least in part on whether the 8-bit output is the multiplicative inverse of the 8-bit input. Other apparatus, methods, and systems are also disclosed.

    SIDE-CHANNEL RESISTANT MULTIPLICATIVELY MASKED AES ENGINE WITH ZERO-VALUE ATTACK DETECTION
    43.
    发明公开
    SIDE-CHANNEL RESISTANT MULTIPLICATIVELY MASKED AES ENGINE WITH ZERO-VALUE ATTACK DETECTION 审中-公开

    公开(公告)号：US20240333471A1

    公开(公告)日：2024-10-03

    申请号：US18190308

    申请日：2023-03-27

    Applicant: Intel Corporation

    Inventor： Raghavan Kumar ,  Sanu Mathew ,  Sachin Taneja

    IPC: H04L9/06

    CPC classification number: H04L9/0631 ,  H04L9/0637

    Abstract: In one embodiment, a method comprises: combining, in a first adder circuit of a cryptographic engine, a round key with masked plaintext to generate an additively masked input; converting, in a first converter of the cryptographic engine, the additively masked input to a multiplicatively masked input; and performing, in a substitution box circuit of the cryptographic engine, a non-linear inverse operation on the multiplicatively masked input when the multiplicatively masked input is non-zero, and performing the non-linear inverse operation on a random non-zero value when the multiplicatively masked input is zero. Other embodiments are described and claimed.

    ODD INDEX PRECOMPUTATION FOR AUTHENTICATION PATH COMPUTATION
    45.
    发明申请
    ODD INDEX PRECOMPUTATION FOR AUTHENTICATION PATH COMPUTATION 有权

    公开(公告)号：US20220131706A1

    公开(公告)日：2022-04-28

    申请号：US17568919

    申请日：2022-01-05

    Applicant: Intel Corporation

    Inventor： Rafael Misoczki ,  Vikram Suresh ,  Santosh Ghosh ,  Manoj Sastry ,  Sanu Mathew ,  Raghavan Kumar

    IPC: H04L9/32 ,  H04L9/08

    Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.

    Odd index precomputation for authentication path computation
    47.
    发明授权
    Odd index precomputation for authentication path computation 有权

    公开(公告)号：US11223483B2

    公开(公告)日：2022-01-11

    申请号：US16456064

    申请日：2019-06-28

    Applicant: Intel Corporation

    Inventor： Rafael Misoczki ,  Vikram Suresh ,  Santosh Ghosh ,  Manoj Sastry ,  Sanu Mathew ,  Raghavan Kumar

    IPC: H04L9/32 ,  H04L9/08

    Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.

    Unified AES-SMS4—Camellia symmetric key block cipher acceleration
    48.
    发明授权
    Unified AES-SMS4—Camellia symmetric key block cipher acceleration 有权

    公开(公告)号：US11121856B2

    公开(公告)日：2021-09-14

    申请号：US16010206

    申请日：2018-06-15

    Applicant: Intel Corporation

    Inventor： Sudhir Satpathy ,  Vikram Suresh ,  Sanu Mathew

    IPC: H04L9/06 ,  G09C1/00 ,  G06F7/72

    Abstract: Disclosed embodiments relate to a unified Advanced Encryption Standard (AES), SMS4, and Camellia (CML) accelerator. In one example, a processor includes fetch circuitry to fetch a cipher instruction specifying an opcode, a datum, and a key, the opcode to specify one of three cryptographic modes and an operation, decode circuitry to decode the fetched cipher instruction, and execution circuitry to respond to the decoded cipher instruction by performing the operation using a selected one of three block ciphers corresponding to the specified cryptographic mode and a unified cipher datapath shared by the three block ciphers, the unified cipher datapath comprising a plurality of hybrid substitution boxes (Sboxes) to perform Galois Field (GF) multiplications and inverse computations, wherein the unified cipher datapath is to implement an eighth-order polynomial isomorphically equivalent to each polynomial used by the three block ciphers by calculating and then combining two fourth-order polynomials.

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