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    Arbiter verification
    41.
    发明授权
    Arbiter verification 有权

    公开(公告)号：US09626465B2

    公开(公告)日：2017-04-18

    申请号：US14920445

    申请日：2015-10-22

    Applicant: Imagination Technologies Limited

    Inventor： Iain Singleton ,  Ashish Darbari ,  John Alexander Osborne Netterville

    IPC: G06F17/50

    CPC classification number: G06F13/364 ,  G06F13/1621 ,  G06F13/3625 ,  G06F13/4252 ,  G06F13/4256 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5045

    Abstract: Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.

    Detecting out-of-bounds violations in a hardware design using formal verification
    43.
    发明授权
    Detecting out-of-bounds violations in a hardware design using formal verification 有权

    公开(公告)号：US12093621B2

    公开(公告)日：2024-09-17

    申请号：US18202929

    申请日：2023-05-28

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari ,  Iain Singleton

    IPC: G06F30/3323 ,  G06F11/07 ,  G06F11/34 ,  G06F30/39

    CPC classification number: G06F30/3323 ,  G06F11/0754 ,  G06F11/3466 ,  G06F30/39

    Abstract: A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.

    DETECTING OUT-OF-BOUNDS VIOLATIONS IN A HARDWARE DESIGN USING FORMAL VERIFICATION
    45.
    发明公开
    DETECTING OUT-OF-BOUNDS VIOLATIONS IN A HARDWARE DESIGN USING FORMAL VERIFICATION 审中-公开

    公开(公告)号：US20240020447A1

    公开(公告)日：2024-01-18

    申请号：US18202929

    申请日：2023-05-28

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari ,  Iain Singleton

    IPC: G06F30/3323 ,  G06F11/07 ,  G06F11/34 ,  G06F30/39

    CPC classification number: G06F30/3323 ,  G06F11/0754 ,  G06F11/3466 ,  G06F30/39

    Abstract: A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.

    OUT-OF-BOUNDS RECOVERY CIRCUIT
    46.
    发明公开
    OUT-OF-BOUNDS RECOVERY CIRCUIT 审中-公开

    公开(公告)号：US20230205621A1

    公开(公告)日：2023-06-29

    申请号：US18114963

    申请日：2023-02-27

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari ,  Iain Singleton

    IPC: G06F11/07 ,  G06F30/30 ,  G06F21/52

    CPC classification number: G06F11/0793 ,  G06F30/30 ,  G06F11/073 ,  G06F21/52 ,  G06F11/0736 ,  G06F11/0754 ,  G06F30/392

    Abstract: Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.

    DETECTING OUT-OF-BOUNDS VIOLATIONS IN A HARDWARE DESIGN USING FORMAL VERIFICATION
    48.
    发明申请
    DETECTING OUT-OF-BOUNDS VIOLATIONS IN A HARDWARE DESIGN USING FORMAL VERIFICATION 有权

    公开(公告)号：US20220138389A1

    公开(公告)日：2022-05-05

    申请号：US17573611

    申请日：2022-01-11

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari ,  Iain Singleton

    IPC: G06F30/3323 ,  G06F11/07 ,  G06F11/34 ,  G06F30/39

    Abstract: A hardware monitor arranged to detect out-of-bounds violations in a hardware design for an electronic device. The hardware monitors include monitor and detection logic configured to monitor the current operating state of an instantiation of the hardware design and detect when the instantiation of the hardware design implements a fetch of an instruction from memory; and assertion evaluation logic configured to evaluate one or more assertions that assert a formal property that compares the memory address of the fetched instruction to an allowable memory address range associated with the current operating state of the instantiation of the hardware design to determine whether there has been an out-of-bounds violation. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design does not cause an instruction to be fetched from an out-of-bounds address.

    OUT-OF-BOUNDS RECOVERY CIRCUIT
    49.
    发明申请
    OUT-OF-BOUNDS RECOVERY CIRCUIT 有权

    公开(公告)号：US20210294690A1

    公开(公告)日：2021-09-23

    申请号：US17338538

    申请日：2021-06-03

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari ,  Iain Singleton

    IPC: G06F11/07 ,  G06F30/30

    Abstract: Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.

    Assessing performance of a hardware design using formal evaluation logic
    50.
    发明授权
    Assessing performance of a hardware design using formal evaluation logic 有权

    公开(公告)号：US10963611B2

    公开(公告)日：2021-03-30

    申请号：US16414594

    申请日：2019-05-16

    Applicant: Imagination Technologies Limited

    Inventor： Ashish Darbari ,  Iain Singleton

    IPC: G06F30/3323 ,  G06F30/30 ,  G06F30/39 ,  G06F11/30 ,  G06F11/34 ,  G06F11/36 ,  G06F119/18

    Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

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