Demodulator for high bit rate transmission and corresponding demodulation method
    41.
    发明授权
    Demodulator for high bit rate transmission and corresponding demodulation method 有权
    用于高比特率传输的解调器和相应的解调方法

    公开(公告)号:US08477680B2

    公开(公告)日:2013-07-02

    申请号:US13108623

    申请日:2011-05-16

    Applicant: Jacques Meyer

    Inventor: Jacques Meyer

    CPC classification number: H04B7/18526

    Abstract: Processing method for modulated data transmitted in the form of multiplexed frames (Frame 1, . . . Frame 10) containing symbols that have a symbol frequency. The method comprises a frame selection processing operation performed at least partly at a working frequency below the symbol frequency, and a demodulation processing operation comprising at least a part performed at the working frequency on the selected frames.

    Abstract translation: 以包含具有符号频率的符号的多路复用帧(帧1,...,帧10)的形式发送的调制数据的处理方法。 该方法包括至少部分地在符号频率以下的工作频率下执行的帧选择处理操作,以及包括在所选择的帧上以工作频率执行的至少一部分的解调处理操作。

    Demodulator for High Bit Rate Transmission and Corresponding Demodulation Method
    42.
    发明申请
    Demodulator for High Bit Rate Transmission and Corresponding Demodulation Method 有权
    用于高比特率传输的解调器和相应的解调方法

    公开(公告)号:US20110286383A1

    公开(公告)日:2011-11-24

    申请号:US13108623

    申请日:2011-05-16

    Applicant: Jacques Meyer

    Inventor: Jacques Meyer

    CPC classification number: H04B7/18526

    Abstract: Processing method for modulated data transmitted in the form of multiplexed frames (Frame 1, . . . Frame 10) containing symbols that have a symbol frequency. The method comprises a frame selection processing operation performed at least partly at a working frequency below the symbol frequency, and a demodulation processing operation comprising at least a part performed at the working frequency on the selected frames.

    Abstract translation: 以包含具有符号频率的符号的多路复用帧(帧1,...,帧10)的形式发送的调制数据的处理方法。 该方法包括至少部分地在符号频率以下的工作频率下执行的帧选择处理操作,以及包括在所选择的帧上以工作频率执行的至少一部分的解调处理操作。

    Receive circuit
    43.
    发明授权
    Receive circuit 有权
    接收电路

    公开(公告)号:US08020080B2

    公开(公告)日:2011-09-13

    申请号:US11729621

    申请日:2007-03-29

    Abstract: A method and a circuit for decoding a coded signal including a first decoding system capable of receiving the coded signal and of providing a first signal comprising portions considered correct and a second decoding system capable of providing a second signal from the coded signal and from portions considered correct of the first signal.

    Abstract translation: 一种用于解码编码信号的方法和电路,包括能够接收编码信号的第一解码系统和提供包括被认为是正确的部分的第一信号,以及能够从编码信号和所考虑的部分提供第二信号的第二解码系统 正确的第一个信号。

    Determination of carrier and symbol frequencies in a signal
    44.
    发明授权
    Determination of carrier and symbol frequencies in a signal 有权
    确定信号中的载波和符号频率

    公开(公告)号:US07865144B2

    公开(公告)日:2011-01-04

    申请号:US11213390

    申请日:2005-08-26

    Applicant: Jacques Meyer

    Inventor: Jacques Meyer

    CPC classification number: H04L27/0014

    Abstract: A method and a device for determining, in a signal, a value of the frequency of a carrier and a value of the frequency of symbols carried by the carrier. A band of the signal is analyzed at three points and the relations between the powers at these points enable determining values of the carrier frequency and of the symbol frequency.

    Abstract translation: 一种用于在信号中确定载波频率的值和由载波携带的符号频率的值的方法和装置。 在三个点处分析信号的频带,并且这些点的功率之间的关系使得能够确定载波频率和符号频率的值。

    Receive circuit
    46.
    发明申请
    Receive circuit 有权
    接收电路

    公开(公告)号:US20070229344A1

    公开(公告)日:2007-10-04

    申请号:US11729621

    申请日:2007-03-29

    Abstract: A method and a circuit for decoding a coded signal including a first decoding system capable of receiving the coded signal and of providing a first signal comprising portions considered correct and a second decoding system capable of providing a second signal from the coded signal and from portions considered correct of the first signal.

    Abstract translation: 一种用于解码编码信号的方法和电路,包括能够接收编码信号的第一解码系统和提供包括被认为是正确的部分的第一信号,以及能够从编码信号和所考虑的部分提供第二信号的第二解码系统 正确的第一个信号。

    Device for estimating a timing correction loop error for a digital demodulator
    47.
    发明申请
    Device for estimating a timing correction loop error for a digital demodulator 有权
    用于估计数字解调器的定时校正回路误差的装置

    公开(公告)号:US20060098763A1

    公开(公告)日:2006-05-11

    申请号:US11270388

    申请日:2005-11-09

    Applicant: Jacques Meyer

    Inventor: Jacques Meyer

    CPC classification number: H04L7/007 H04L7/0029 H04L2027/003 H04L2027/0057

    Abstract: A device for providing a digital error signal, for a timing correction loop of a digital demodulator for digital transmission by phase modulation or amplitude and phase modulation, the device successively receiving pairs of digital signals representative of the components of complex signals, and having circuitry for providing a difference signal representative of the difference between the modulus of the complex signal corresponding to the last received pair of digital signals and the modulus of the complex signal corresponding to the previously-received pair of digital signals; circuitry for providing a weighting factor which depends on the angle between the complex signal corresponding to the last received pair of digital signals and the complex signal corresponding to the previously-received pair of digital signals; and circuitry for providing the error signal proportional to the product of the difference signal and of the weighting factor.

    Abstract translation: 一种用于为通过相位调制或幅度和相位调制进行数字传输的数字解调器的定时校正回路提供数字误差信号的装置,该装置连续地接收代表复信号分量的数字信号对,并具有用于 提供表示对应于最后接收的数字信号对的复数信号的模数与对应于先前接收到的数字信号对的复数信号的模数之间的差的差信号; 用于提供取决于对应于最后接收的数字信号对的复信号与对应于先前接收到的一对数字信号的复信号之间的角度的加权因子的电路; 以及用于提供与差分信号和加权因子的乘积成比例的误差信号的电路。

    Determination of carrier and symbol frequencies in a signal
    48.
    发明申请
    Determination of carrier and symbol frequencies in a signal 有权
    确定信号中的载波和符号频率

    公开(公告)号:US20060044477A1

    公开(公告)日:2006-03-02

    申请号:US11213390

    申请日:2005-08-26

    Applicant: Jacques Meyer

    Inventor: Jacques Meyer

    CPC classification number: H04L27/0014

    Abstract: A method and a device for determining, in a signal, a value of the frequency of a carrier and a value of the frequency of symbols carried by the carrier. A band of the signal is analyzed at three points and the relations between the powers at these points enable determining values of the carrier frequency and of the symbol frequency.

    Abstract translation: 一种用于在信号中确定载波频率的值和由载波携带的符号频率的值的方法和装置。 在三个点处分析信号的频带,并且这些点的功率之间的关系使得能够确定载波频率和符号频率的值。

    Demodulator synchronization loop lock-in detection circuit
    49.
    发明授权
    Demodulator synchronization loop lock-in detection circuit 有权
    解调器同步回路锁定检测电路

    公开(公告)号:US06639952B1

    公开(公告)日:2003-10-28

    申请号:US09333351

    申请日:1999-06-15

    Applicant: Jacques Meyer

    Inventor: Jacques Meyer

    CPC classification number: H04L27/2273 H04L2027/003 H04L2027/0053

    Abstract: A method for detecting the lock-in of a loop that synchronizes an internal clock on the transmission of value pairs provided by a demodulator. According to the method, a module of a vector that has as components the values of one of the value pairs is calculated, and the module is compared with a threshold that is smaller than a theoretical module. The locked-in condition is determined according to the ratio of the number of modules found to be greater than or smaller than the threshold to the total number of modules. In one preferred method, the threshold is incremented by a first value if the module is greater than the threshold and is decremented by a second value if the module is less than the threshold. A lock-in detection circuit for detecting the lock-in of a loop is also provided. A calculation circuit calculates a module of a vector that has as components the values of one of the value pairs. A register stores a threshold and a comparator compares the stored threshold with the calculated module. A modification circuit modifies the stored threshold based on the comparison result, and an analysis circuit analyzes the stored threshold to determine the locked-in condition.

    Abstract translation: 一种用于检测在由解调器提供的值对的传输上同步内部时钟的环路的锁定的方法。 根据该方法,计算具有作为值对之一的值的分量的向量的模块,并将模块与小于理论模块的阈值进行比较。 锁定状态根据发现大于或小于阈值的模块数与模块总数之比确定。 在一个优选方法中,如果模块大于阈值,则阈值增加第一值,并且如果模块小于阈值则递减第二值。 还提供了用于检测环路锁定的锁定检测电路。 计算电路计算具有作为值对之一的值的分量的向量的模块。 寄存器存储阈值,比较器将存储的阈值与计算出的模块进行比较。 修改电路根据比较结果修改存储的阈值,并且分析电路分析存储的阈值以确定锁定状态。

    Intermediary frequency input QPSK demodulator
    50.
    发明授权
    Intermediary frequency input QPSK demodulator 有权
    中间频率输入QPSK解调器

    公开(公告)号:US06614856B1

    公开(公告)日:2003-09-02

    申请号:US09340905

    申请日:1999-06-28

    Applicant: Jacques Meyer

    Inventor: Jacques Meyer

    CPC classification number: H04L27/2338 H04L27/22

    Abstract: The present invention relates to a demodulator provided to extract two signals modulated in phase quadrature from an intermediary frequency signal, including two analog-to-digital converters receiving the intermediary frequency signal and clocked in phase opposition by a clock at a frequency smaller than the intermediary frequency, at least equal to the bandwidth of the modulated signals, and such that the central frequency of one of the aliased spectrums of the signal converted into digital is substantially equal to half the clock frequency; and two multipliers respectively receiving the outputs of the analog-to-digital converters and receiving at the same time a sequence of values 1, −1, 1, −1, 1 . . . at the clock rate.

    Abstract translation: 本发明涉及一种解调器,用于从中间频率信号中提取出相位正交调制的两个信号,包括两个接收中间频率信号的模数转换器,并以相对于中间频率的频率进行相位反相的时钟 频率,至少等于调制信号的带宽,并且使得转换成数字的信号的混叠频谱之一的中心频率基本上等于时钟频率的一半; 和两个乘法器分别接收模数转换器的输出并同时接收值1,-1,1,-1,1的序列。 。 。 以时钟速率。

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