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49 条记录 (耗时 0.035 秒)

    Schottky-clamped bipolar transistor with reduced self heating
    42.
    发明授权
    Schottky-clamped bipolar transistor with reduced self heating 有权
    肖特基钳位的双极晶体管，自发热减少

    公开(公告)号：US08455980B2

    公开(公告)日：2013-06-04

    申请号：US13178629

    申请日：2011-07-08

    申请人： Jeffrey A. Babcock

    发明人： Jeffrey A. Babcock

    IPC分类号： H01L29/66

    CPC分类号： H01L21/84 ,  H01L27/0664 ,  H01L27/1203

    摘要： The self heating of a high-performance bipolar transistor that is formed on a fully-isolated single-crystal silicon region of a silicon-on-insulator (SOI) structure is substantially reduced by forming a Schottky structure in the same fully-isolated single-crystal silicon region as the bipolar transistor is formed.

    摘要翻译： 形成在绝缘体上硅（SOI）结构的完全隔离的单晶硅区域上的高性能双极晶体管的自加热通过在相同的完全隔离单晶硅中形成肖特基结构而大大降低， 形成作为双极晶体管的晶体硅区域。

    Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structures
    46.
    发明授权
    Schottky junction-field-effect-transistor (JFET) structures and methods of forming JFET structures 有权
    肖特基结场效应晶体管（JFET）结构和形成JFET结构的方法

    公开(公告)号：US08207559B2

    公开(公告)日：2012-06-26

    申请号：US12498141

    申请日：2009-07-06

    申请人： Jeffrey A. Babcock ,  Natalia Lavrovskaya ,  Saurabh Desai ,  Alexei Sadovnikov ,  Zia Alan Shafi

    发明人： Jeffrey A. Babcock ,  Natalia Lavrovskaya ,  Saurabh Desai ,  Alexei Sadovnikov ,  Zia Alan Shafi

    IPC分类号： H01L29/66

    CPC分类号： H01L27/095 ,  H01L27/0207 ,  H01L29/1029 ,  H01L29/1058 ,  H01L29/808 ,  H01L29/812

    摘要： In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material, to form the gate contact of the JFET. The structural concepts can also be applied to a standard JFET that uses N− type or P− type dopants to form the gate of the JFET. In addition, the structures allow for an improved JFET linkup with buried linkup contacts allowing improved noise and reliability performance for both conventional diffusion (N− and P− channel) JFET structures and for Schottky JFET structures. In accordance with another aspect of the invention, the gate poly, as found in a standard CMOS or BiCMOS process flow, is used to perform the linkup between the source and the junction gate and/or between the drain and the junction gate of a junction filed effect transistor (JFET). Use of a bias on the gate linkup of the JFET allows an additional tuning knob for the JFET that can be optimized to trade off breakdown characteristics with reduced on resistance. In accordance with yet another aspect of the invention, a patterned buried layer is used to form the back gate control for a junction field effect transistor (JFET). The structure allows a layout or buried layer pattern change to adjust the pinch-off voltage of the JFET structure. Vertical and lateral diffusion of the buried layer is used to adjust the JFET operating parameters with a simple change in the buried layer patterns. In addition, the structures allow for increased breakdown voltage by leveraging charge sharing concepts and improving channel confinement for power JFET structures. These concepts can also be applied to both N− channel and P− channel diffusion JFETs and to Schottky JFET structures.

    摘要翻译： 根据本发明的一个方面，使用硅化钴或其它肖特基材料制造肖特基结场效应晶体管（JFET），以形成JFET的栅极接触。 结构概念也可以应用于使用N型或P-型掺杂剂形成JFET栅极的标准JFET。 此外，这些结构允许改进的JFET与嵌入式连接触点连接，从而可以改善常规扩散（N和P沟道）JFET结构和肖特基JFET结构的噪声和可靠性性能。 根据本发明的另一方面，如标准CMOS或BiCMOS工艺流程中所发现的栅极聚合体用于执行源极和结栅极之间和/或在结的漏极和结栅之间的连接 场效应晶体管（JFET）。 在JFET的栅极连接上使用偏置可以为JFET提供一个额外的调谐旋钮，该调谐旋钮可以优化，以降低导通电阻的击穿特性。 根据本发明的另一方面，图案化掩埋层用于形成结型场效应晶体管（JFET）的背栅极控制。 该结构允许布局或掩埋层图案改变以调节JFET结构的夹断电压。 掩埋层的垂直和横向扩散用于通过掩埋层图案的简单变化来调节JFET操作参数。 此外，这些结构允许通过利用电荷共享概念并改善功率JFET结构的通道限制来增加击穿电压。 这些概念也可以应用于N沟道和P沟道扩散JFET以及肖特基JFET结构。

    Method of forming a semiconductor die with reduced RF attenuation
    49.
    发明授权
    Method of forming a semiconductor die with reduced RF attenuation 有权
    以减少RF衰减形成半导体管芯的方法

    公开(公告)号：US07902013B1

    公开(公告)日：2011-03-08

    申请号：US12551263

    申请日：2009-08-31

    申请人： Jeffrey A. Babcock ,  Yongseon Koh

    发明人： Jeffrey A. Babcock ,  Yongseon Koh

    IPC分类号： H01L21/338

    CPC分类号： H01L21/761 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An electrically floating region is formed in the top surface of a semiconductor wafer to implement a radio frequency (RF) blocking structure. The RF blocking structure lies below the metal pads and traces that carry an RF signal in a metal interconnect structure to substantially reduces the attenuation of the RF signal.

    摘要翻译： 在半导体晶片的顶表面上形成电浮置区，以实现射频（RF）阻挡结构。 RF阻挡结构位于金属焊盘和迹线之下，金属焊盘和迹线在金属互连结构中承载RF信号，以显着降低RF信号的衰减。