公开(公告)号：US09966945B2

公开(公告)日：2018-05-08

申请号：US15212126

申请日：2016-07-15

申请人： Panasonic Corporation

发明人： Shinji Ujita ,  Hiroshi Inada ,  Tatsuo Morita

IPC分类号： H03B1/00 ,  H03K3/00 ,  H03K17/687 ,  H01L29/778 ,  H01L27/095 ,  H01L27/098 ,  H01L29/20 ,  H01L27/088 ,  H01L23/482 ,  H01L23/00 ,  H03K17/0412 ,  H03K17/16 ,  H01L27/06 ,  H02M3/158 ,  H01L23/522 ,  H01L29/417 ,  H01L29/10

CPC分类号： H03K17/6871 ,  H01L23/4824 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L27/0605 ,  H01L27/0883 ,  H01L27/095 ,  H01L27/098 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/7786 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06051 ,  H01L2224/06177 ,  H01L2224/131 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H02M3/158 ,  H02M3/1588 ,  H03K17/04123 ,  H03K17/162 ,  H03K17/6877 ,  H03K2017/6875 ,  H03K2217/0063 ,  H03K2217/0072 ,  Y02B70/1466 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/014

摘要： A semiconductor device is provided which realizes speed-up and cost reduction. The semiconductor device has a high side gate driver including a depression type FET and an enhancement type FET, a low side gate driver including a depression type FET and an enhancement type FET, and a high side power FET and a low side power FET as field-effect transistors, in which the high side gate driver, the low side gate driver, the high side power FET and the low side power FET are integrated in the same chip.

公开(公告)号：US20180090476A1

公开(公告)日：2018-03-29

申请号：US15681721

申请日：2017-08-21

申请人： FUJITSU LIMITED

发明人： Youichi KAMADA

IPC分类号： H01L27/02 ,  H01L27/095 ,  H01L29/40 ,  H01L29/778 ,  H01L21/8232 ,  H01L29/66 ,  H01L29/417 ,  H03F3/213 ,  H03F1/30 ,  H02M5/458

CPC分类号： H01L27/0211 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/0272 ,  H01L21/0274 ,  H01L21/8232 ,  H01L27/0248 ,  H01L27/095 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H02M1/4225 ,  H02M3/33592 ,  H02M3/337 ,  H02M5/458 ,  H02M7/003 ,  H02M2001/007 ,  H03F1/306 ,  H03F1/3247 ,  H03F3/195 ,  H03F3/213 ,  H03F3/245 ,  H03F2200/451 ,  Y02B70/126 ,  Y02B70/1475

摘要： A compound semiconductor device includes transistors each including a gate electrode, a source electrode, and a drain electrode, wherein out of the transistors, a transistor whose temperature becomes higher during operation has a higher withstand voltage prior to temperature rise due to the operation.

公开(公告)号：US09818692B2

公开(公告)日：2017-11-14

申请号：US15078023

申请日：2016-03-23

申请人： GaN Systems Inc.

发明人： John Roberts ,  Greg P. Klowak ,  Cameron McKnight-MacNeil

IPC分类号： H01L23/528 ,  H01L21/66 ,  H01L27/095 ,  H01L29/40 ,  H01L29/778 ,  H01L23/373 ,  H01L29/20 ,  H01L29/06 ,  H01L23/36

CPC分类号： H01L23/528 ,  H01L22/32 ,  H01L23/36 ,  H01L23/3737 ,  H01L27/095 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/7786

摘要： Devices and systems comprising high current/high voltage GaN semiconductor devices are disclosed. A GaN die, comprising a lateral GaN transistor, is sandwiched between an overlying header and an underlying composite thermal dielectric layer. Fabrication comprises providing a conventional GaN device structure fabricated on a low cost silicon substrate (GaN-on-Si die), mechanically and electrically attaching source, drain and gate contact pads of the GaN-on-Si die to corresponding contact areas of conductive tracks of the header, then entirely removing the silicon substrate. The exposed substrate-surface of the epi-layer stack is coated with the composite dielectric thermal layer. Preferably, the header comprises a ceramic dielectric support layer having a CTE matched to the GaN epi-layer stack. The thermal dielectric layer comprises a high dielectric strength thermoplastic polymer and a dielectric filler having a high thermal conductivity. This structure offers improved electrical breakdown resistance and effective thermal dissipation compared to conventional GaN-on-Si device structures.

公开(公告)号：US20170271333A1

公开(公告)日：2017-09-21

申请号：US15611824

申请日：2017-06-02

申请人： SONY CORPORATION

发明人： MASAHIRO MITSUNAGA

IPC分类号： H01L27/095 ,  H01L21/28 ,  H01L41/25 ,  H01L41/08 ,  H01L29/66 ,  H01L21/8252 ,  H01L29/205 ,  H01L29/10 ,  H01L29/778

CPC分类号： H01L27/095 ,  H01L21/28 ,  H01L21/8252 ,  H01L29/1066 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7785 ,  H01L29/7786 ,  H01L41/0815 ,  H01L41/25

摘要： A semiconductor device includes a buffer layer formed with a semiconductor adapted to produce piezoelectric polarization, and a channel layer stacked on the buffer layer, wherein a two-dimensional hole gas, generated in the channel layer by piezoelectric polarization of the buffer layer, is used as a carrier of the channel layer. On a complementary semiconductor device, the semiconductor device described above and an n-type field effect transistor are formed on the same compound semiconductor substrate. Also, a level shift circuit is manufactured by using the semiconductor device. Further, a semiconductor device manufacturing method includes forming a compound semiconductor base portion, forming a buffer layer on the base portion, forming a channel layer on the buffer layer, forming a gate on the channel layer, and forming a drain and source with the gate therebetween on the channel layer.

公开(公告)号：US09685345B2

公开(公告)日：2017-06-20

申请号：US14084335

申请日：2013-11-19

申请人： Bruce M. Green ,  Darrell G. Hill ,  Karen E. Moore

发明人： Bruce M. Green ,  Darrell G. Hill ,  Karen E. Moore

IPC分类号： H01L29/15 ,  H01L21/311 ,  H01L29/872 ,  H01L29/66 ,  H01L23/544 ,  H01L29/47 ,  H01L29/778 ,  H01L27/06 ,  H01L27/095 ,  H01L21/027 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L21/0272 ,  H01L21/31111 ,  H01L23/544 ,  H01L27/0605 ,  H01L27/095 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/66143 ,  H01L29/66431 ,  H01L29/812 ,  H01L29/872 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a Schottky metal layer disposed over the substrate adjacent the gate electrode. The Schottky metal layer includes a Schottky contact electrically coupled to the channel which provides a Schottky junction and at least one alignment mark disposed over the semiconductor substrate. A method for fabricating the semiconductor device includes creating an isolation region that defines an active region along an upper surface of a semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and forming a Schottky metal layer over the semiconductor substrate. Forming the Schottky metal layer includes forming at least one Schottky contact electrically coupled to the channel and providing a Schottky junction, and forming an alignment mark in the isolation region.

公开(公告)号：US09536803B2

公开(公告)日：2017-01-03

申请号：US14847558

申请日：2015-09-08

申请人： RF Micro Devices, Inc.

发明人： David Charles Sheridan ,  Robert Charles Dry ,  Don Willis

IPC分类号： H01L23/34 ,  H01L25/07 ,  H05K7/20 ,  H01L27/095 ,  H01L27/088 ,  H01L29/10 ,  H01L23/373 ,  H01L23/367 ,  H01L23/498 ,  H01L29/423

CPC分类号： H01L23/345 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/49827 ,  H01L23/49844 ,  H01L25/072 ,  H01L27/088 ,  H01L27/095 ,  H01L29/1079 ,  H01L29/4232 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/73265 ,  H05K7/205 ,  H05K7/20963 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated power module having a depletion mode device and an enhancement mode device that is configured to prevent an accidental on-state condition for the depletion mode device during a gate signal loss is disclosed. In particular, the disclosed integrated power module is structured to provide improved isolation and thermal conductivity. The structure includes a substrate having a bottom drain pad for the depletion mode device disposed on the substrate and an enhancement mode device footprint-sized cavity that extends through the substrate to the bottom drain pad. A thermally conductive and electrically insulating slug substantially fills the cavity to provide a higher efficient thermal path between the enhancement mode device and the bottom drain pad for the depletion mode device.

摘要翻译： 具有耗尽型器件和增强型器件的集成电源模块被配置为在栅极信号丢失期间防止耗尽型器件的意外导通状态。 特别地，所公开的集成功率模块被构造成提供改进的隔离和导热性。 该结构包括具有用于耗尽型器件的底部漏极焊盘的衬底，其设置在衬底上，以及增强模式器件占位面积尺寸的空腔，其延伸穿过衬底到底部漏极焊盘。 导热和电绝缘的芯块基本上填充空腔，以在增强模式器件和用于耗尽型器件的底部漏极焊盘之间提供更高效的热路径。

公开(公告)号：US20160190127A1

公开(公告)日：2016-06-30

申请号：US15063310

申请日：2016-03-07

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Jun-De Jin ,  Tzu-Jin Yeh ,  Chewn-Pu Jou

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/812 ,  H01L29/78 ,  H01L21/8236 ,  H01L29/66

CPC分类号： H01L27/0883 ,  H01L21/8236 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/095 ,  H01L29/0649 ,  H01L29/66666 ,  H01L29/66848 ,  H01L29/7827 ,  H01L29/812 ,  H03F1/223 ,  H03F3/213

摘要： A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a Schottky MOSFET formed in an N-Well in the same P-Substrate with a horizontal or a vertical channel between the source, drain, and gate electrodes of the Schottky MOSFET. The source node of the enhancement MOSFET and source node of the Schottky MOSFET are connected together to form the power cell.

摘要翻译： 为RF功率放大器设计的功率单元包括形成在P基板中的P阱中的增强型MOSFET和形成在相同P基板中的N阱中的肖特基MOSFET，源极之间具有水平或垂直通道 ，漏极和栅电极。 增强型MOSFET的源节点和肖特基MOSFET的源极节点连接在一起形成功率单元。

公开(公告)号：US09318487B2

公开(公告)日：2016-04-19

申请号：US13937542

申请日：2013-07-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jun-De Jin ,  Tzu-Jin Yeh ,  Chewn-Pu Jou

IPC分类号： H01L27/088 ,  H03F1/22 ,  H01L21/8238 ,  H01L27/095 ,  H03F3/213 ,  H01L27/092

CPC分类号： H01L27/0883 ,  H01L21/8236 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/095 ,  H01L29/0649 ,  H01L29/66666 ,  H01L29/66848 ,  H01L29/7827 ,  H01L29/812 ,  H03F1/223 ,  H03F3/213

摘要： A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a depletion or Schottky MOSFET formed in an N-Well in the same P-Substrate with a horizontal or a vertical channel between the source, drain, and gate electrodes of the depletion or Schottky MOSFET. The source node of the enhancement MOSFET and source node of the depletion or Schottky MOSFET are connected together to form the power cell.

摘要翻译： 为RF功率放大器设计的功率单元包括形成在P基板中的P阱中的增强型MOSFET和形成在相同P-基板中的N阱中的耗尽或肖特基MOSFET，其中水平或垂直通道介于 耗尽或肖特基MOSFET的源极，漏极和栅电极。 增强MOSFET的源节点和耗尽型或肖特基MOSFET的源极节点连接在一起形成功率单元。

公开(公告)号：US20150325675A1

公开(公告)日：2015-11-12

申请号：US14573708

申请日：2014-12-17

申请人： Advanced Semiconductor Manufacturing Corporation Limited

发明人： Xizheng Wang

IPC分类号： H01L29/66 ,  H01L29/872

CPC分类号： H01L21/0495 ,  H01L21/8234 ,  H01L27/0629 ,  H01L27/095 ,  H01L29/0661 ,  H01L29/66143 ,  H01L29/8725

摘要： A method for yield improvement of trench MOS barrier Schottky (TMBS) devices includes: forming a plurality of trenches in a substrate; forming a gate dielectric layer over a surface of the substrate and inner surfaces of the trenches; forming gates in the trenches; forming a first barrier dielectric layer, a second barrier dielectric layer and an intermediate dielectric layer over the trenches; etching the intermediate dielectric layer with the second barrier dielectric layer serving as an etch stop layer to form a window for forming contact holes; etching a portion of the second barrier dielectric layer within the window using the first barrier dielectric layer as an etch stop layer; and etching in the window to remove a portion of the first barrier dielectric layer overlying the gates and a portion of the gate dielectric layer overlying the substrate.

摘要翻译： 沟槽MOS势垒肖特基（TMBS）器件的产率改进方法包括：在衬底中形成多个沟槽; 在所述基板的表面和所述沟槽的内表面上形成栅极电介质层; 在沟渠中形成门; 在所述沟槽上形成第一阻挡介电层，第二阻挡介电层和中间介电层; 用作为蚀刻停止层的第二阻挡介电层蚀刻中间介电层，以形成用于形成接触孔的窗口; 使用第一势垒介电层作为蚀刻停止层来蚀刻窗口内的第二势垒介电层的一部分; 以及在窗口中蚀刻以去除覆盖在栅极上的第一势垒介电层的一部分和覆盖衬底的栅极电介质层的一部分。

公开(公告)号：US09165922B2

公开(公告)日：2015-10-20

申请号：US14015986

申请日：2013-08-30

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Akira Yoshioka ,  Yasunobu Saito ,  Hidetoshi Fujimoto ,  Takeshi Uchihara ,  Naoko Yanase ,  Toshiyuki Naka ,  Tetsuya Ohno ,  Tasuku Ono

IPC分类号： H01L27/06 ,  H01L27/095

CPC分类号： H01L27/0629 ,  H01L27/095 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/00 ,  H01L2924/00014

摘要： According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode.

摘要翻译： 根据实施例，半导体器件包括导电衬底，肖特基势垒二极管和场效应晶体管。 肖特基势垒二极管安装在导电基板上，并包括阳极电极和阴极电极。 阳极电极与导电性基板电连接。 场效应晶体管安装在导电基板上，包括源电极，漏电极和栅电极。 场效应晶体管的源电极电连接到肖特基势垒二极管的阴极。 场效晶体管的栅电极与肖特基势垒二极管的阳极电连接。