公开(公告)号：US07073144B2

公开(公告)日：2006-07-04

申请号：US10825148

申请日：2004-04-15

申请人： Charles Jay Alpert ,  Gi-Joon Nam ,  Paul Gerard Villarrubia ,  Mehmet Can Yildiz

发明人： Charles Jay Alpert ,  Gi-Joon Nam ,  Paul Gerard Villarrubia ,  Mehmet Can Yildiz

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method of assessing the stability of a placement tool used in designing the physical layout of an integrated circuit chip, by constructing different layouts of cells using the placement tool with different sets of input parameters, and calculating a stability value based on the movement of respective cell locations between the layouts. The stability value can be normalized based on cell locations in a random placement. One stability metric measures absolute movement of individual cells in the layouts, weighted by cell area. The cell movements can be squared in calculating the stability value. Another stability metric measures the relative movement of cells with respect to their nets. Shifting of cells and symmetric reversal of cells about a net center does not contribute to this relative movement, but spreading of cells and rotation of cells with respect to the net center does contribute to the relative movement. Relative cell movements can again be squared in calculating the stability value. Many different layouts can be designed using the same placement tool with a range of different input parameters and different movement metrics to build a collection of comparative values that can be used to identify stability characteristics for that tool.

摘要翻译： 一种评估用于设计集成电路芯片的物理布局的放置工具的稳定性的方法，通过使用具有不同输入参数集合的放置工具构造不同的单元布局，以及基于相应的运动来计算稳定性值 单元格位置之间的布局。 稳定性值可以根据随机位置中的单元格位置进行归一化。 一个稳定度度量衡量单元格在布局中的绝对运动，由单元格区域加权。 在计算稳定性值时，单元格移动可以平方。 另一个稳定度量度衡量细胞相对于网的相对运动。 细胞的移位和细胞对网络中心的对称反转对这种相对运动没有贡献，但是细胞的扩散和细胞的相对于网络中心的旋转确实有助于相对运动。 在计算稳定性值时，相对单元移动可以再次平方。 可以使用具有一系列不同输入参数和不同运动度量的相同放置工具来设计许多不同的布局，以构建可用于识别该工具的稳定性特征的比较值集合。

公开(公告)号：US07031583B2

公开(公告)日：2006-04-18

申请号：US10979585

申请日：2004-11-02

申请人： Do-Hyun Park ,  Gi-Joon Nam

发明人： Do-Hyun Park ,  Gi-Joon Nam

IPC分类号： G02B6/02 ,  G02B6/22 ,  G02B6/44 ,  G02B6/16

CPC分类号： G02B6/443

摘要： Disclosed are an optical fiber unit in which at least 1-core optical fiber is mounted in and protected by a buffer tube, and an optical cable including the optical fiber unit. The buffer tube is made of a mixture, which includes a composite resin including a resin selected from polyolefin polymer, nitrile rubber and their mixture, and plasticized polyvinylchloride; and an inorganic additive, wherein, in a stress-strain curve of the buffer tube, a modulus is 5 to 50 kgf/mm2 in a linear region with an elongation less than 1% and a tan δ is less than 0.5 at 30° C. The buffer tube of the optical fiber unit may be very usefully applied to an optical cable because it may be easily cut out to ensure easy contact and gives excellent elasticity without being crushed by lateral pressure.

摘要翻译： 公开了一种光纤单元，其中至少1芯光纤安装在缓冲管中并由缓冲管保护，以及包括光纤单元的光缆。 缓冲管由混合物制成，其包括包含选自聚烯烃聚合物，丁腈橡胶及其混合物的树脂和增塑聚氯乙烯的复合树脂; 和无机添加剂，其中在缓冲管的应力 - 应变曲线中，在伸长率小于1％的线性区域中的模量为5至50kgf / mm 2，并且tanδ 在30℃下小于0.5。光纤单元的缓冲管可以非常有用地应用于光缆，因为它可以容易地切割以确保容易的接触并且提供优异的弹性而不被横向压力压碎。

公开(公告)号：US20060031804A1

公开(公告)日：2006-02-09

申请号：US10996293

申请日：2004-11-22

申请人： Charles Alpert ,  Gi-Joon Nam ,  Sherief Reda ,  Paul Villarrubia

发明人： Charles Alpert ,  Gi-Joon Nam ,  Sherief Reda ,  Paul Villarrubia

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/50

摘要： A placement technique for designing a layout of an integrated circuit by calculating clustering scores for different pairs of objects in the layout based on connections of two objects in a given pair and the sizes of the two objects, then grouping at least one of the pairs of objects into a cluster based on the clustering scores, partitioning the objects as clustered and ungrouping the cluster after partitioning. The pair of objects having the highest clustering score are grouped into the cluster, and the clustering score is directly proportional to the total weight of connections between the two objects in the respective pair. The clustering scores are preferably inserted in a binary heap to identify the highest clustering score. After grouping, the clustering score for any neighboring object of a clustered object is marked to indicate that the clustering score is invalid and must be recalculated. The calculating and grouping are then repeated iteratively based on the previous clustered layout. Cluster growth can be controlled indirectly, or controlled directly by imposing an upper bound on cluster size.

摘要翻译： 一种用于通过基于给定对中的两个对象的连接和两个对象的大小的布局来计算布局中的不同对对象的聚类分数来设计集成电路的布局的布局技术，然后将至少一个对 对象基于聚类分数进入群集，将对象分区为群集，并在分区后取消分组群集。 具有最高聚类分数的一对对象被分组到聚类中，并且聚类分数与相应对中两个对象之间的连接的总权重成正比。 聚类分数优选插入二进制堆中以识别最高聚类分数。 分组后，将聚类对象的任何邻近对象的聚类分数标记为表示聚类分数无效并且必须重新计算。 然后基于先前的聚类布局迭代地重复计算和分组。 群集增长可以间接控制，也可以通过对群集大小施加上限直接控制。

公开(公告)号：US20140007036A1

公开(公告)日：2014-01-02

申请号：US13539440

申请日：2012-06-30

申请人： Charles J. Alpert ,  Myung-Chul Kim ,  Gi-Joon Nam ,  Shyam Ramji ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Myung-Chul Kim ,  Gi-Joon Nam ,  Shyam Ramji ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： After a global placement phase of physical design of an integrated circuit, a data processing system iteratively refines local placement of a plurality of modules comprising the integrated circuit within a die area based on density of the plurality of modules and separately refines local wirelength for the plurality of modules in individual subareas among a plurality of subareas of the die area. The data processing system thereafter performs detailed placement of modules in the plurality of subareas.

摘要翻译： 在集成电路的物理设计的全局放置阶段之后，数据处理系统基于多个模块的密度迭代地将包括该集成电路的多个模块的本地放置精细化，并单独地对多个模块中的局部线长进行精细化 在模具区域的多个子区域中的各个子区域中的模块。 此后，数据处理系统在多个子区域中执行模块的详细布置。

公开(公告)号：US20130326455A1

公开(公告)日：2013-12-05

申请号：US13485828

申请日：2012-05-31

申请人： Charles J. Alpert ,  Gi-Joon Nam ,  Chin Ngai Sze ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Gi-Joon Nam ,  Chin Ngai Sze ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5068 ,  G06F17/5081

摘要： An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.

摘要翻译： 改进的电路设计系统可以包括计算机处理器，以通过物理合成来执行电路的放置。 该系统还可以包括控制器，用于计算电路的至少一个选定元件的优选位置，并且计算每个选定元件的放置约束。 该系统可以进一步包括通过用放置约束执行另一轮物理合成而产生的电路的更新设计。

公开(公告)号：US08245173B2

公开(公告)日：2012-08-14

申请号：US12359369

申请日：2009-01-26

申请人： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

发明人： Gi-Joon Nam ,  Shyam Ramji ,  Taraneh Taghavi ,  Paul G. Villarrubia

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F9/5066

摘要： Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.

摘要翻译： 区域约束对象放置的并行处理调度在不同的平衡方案之间进行选择。 对于少量的移动端口，通过平衡可放置对象来分配计算。 对于每次移动的少量对象，通过平衡移动端口分配计算。 如果每次移动都有大量的移动和对象，则处理器之间的对象和移动对象都是平衡的。 对于对象平衡，移动端口被分配给一个处理器，直到处理器的对象的摊销数量超过理想数量以上的第一个限制，或者下一个移动端口将提高超过第二个更大限制的对象数量。 对于对象和移动平衡，移动排列按降序排列，然后按顺序分配给主机处理器，连续回合，同时在每轮之后反转处理器顺序。 本发明提供多项式时间的时间表，同时保持高质量的结果。

公开(公告)号：US20120124539A1

公开(公告)日：2012-05-17

申请号：US12947445

申请日：2010-11-16

申请人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David A. Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/62

摘要： A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.

摘要翻译： 提供了一种用于通过本地时钟缓冲器控制优化进行码头优化的物理综合工具。 物理合成流程包括延迟时钟路由的曝光，直到时钟优化放置阶段为止。 物理综合工具克隆了第一个本地时钟缓冲区。 然后，物理综合工具对整个设计运行时序分析，以计算这一必然破坏性步骤的影响。 在克隆本地时钟缓冲器之后，物理综合工具增加了一个额外的优化步骤来对驱动本地时钟缓冲器的控制信号进行目标。 该优化步骤可以包括锁存克隆，定时驱动放置，缓冲器插入和重新供电。 该流程减轻了高扇出网络，并显着提高了进入时钟优化布局的时间。 放置后，物理综合工具将锁存器和本地时钟缓冲器固定到位，插入时钟路由并释放本地时钟缓冲区。

公开(公告)号：US08108819B2

公开(公告)日：2012-01-31

申请号：US12420156

申请日：2009-04-08

申请人： Charles Jay Alpert ,  Gi-Joon Nam ,  Jarrod Alexander Roy ,  Natarajan Vishvanathan

发明人： Charles Jay Alpert ,  Gi-Joon Nam ,  Jarrod Alexander Roy ,  Natarajan Vishvanathan

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F2217/08

摘要： A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the cells including electronic components, wires, and pins defined for interconnections of the IC. An initial placement corresponding to the design is received. A characteristic of the initial placement is estimated, which may include congestion, pin density, or both in an area of the initial placement. A transformation is performed on a part of the initial placement including the area to improve the characteristic. If the characteristic has improved in the transformed placement, a final placement corresponding to the transformed placement is produced. The transformation may be any combination of resizing an object, weighting a connection, clustering a plurality of objects, shortening of a route taken by a wire, and straightening a bend in a wire in the initial placement.

摘要翻译： 在说明性实施例中提供了用于在集成电路设计中改进的对象放置的方法，系统和计算机可用程序产品。 IC设计包括电池，电池包括电子元件，电线和为IC的互连而定义的引脚。 收到与设计相对应的初始放置。 估计初始放置的特征，其可以包括初始放置区域中的拥塞，针密度或两者。 在初始位置的一部分上进行变换，包括改善特征的区域。 如果转换后的位置的特征有所改善，则会生成与转换的位置对应的最终位置。 该变换可以是调整对象的大小，加权连接，​​聚集多个对象，缩短由线引导的路线以及在初始放置中矫正线中的弯曲的任何组合。

公开(公告)号：US20110073348A1

公开(公告)日：2011-03-31

申请号：US12518062

申请日：2007-11-08

申请人： Chan-Yong Park ,  Bong-Kwon Cho ,  Gi-Joon Nam ,  Hyoung-Koog Lee ,  Jung-Won Park ,  Dae-Sung Lee

发明人： Chan-Yong Park ,  Bong-Kwon Cho ,  Gi-Joon Nam ,  Hyoung-Koog Lee ,  Jung-Won Park ,  Dae-Sung Lee

IPC分类号： H01B11/18

CPC分类号： H01B11/1808

摘要： A coaxial cable includes a central conductor made of cylindrical conductive material with conductivity greater than 100% and smaller than 104%, the central conductor having a thickness greater than 0.1 mm and smaller than 0.5 mm; a dielectric layer surrounding the central conductor and made of insulating material; an outer conductor surrounding the dielectric layer and made of conductive material with conductivity greater than 97% and smaller than 105% and a thickness greater than 0.24 mm and smaller than 0.35 mm; and an outer jacket surrounding the outer conductor. This coaxial cable allows stable transmission of signal even at a high frequency.

摘要翻译： 同轴电缆包括由导电率大于100％且小于104％的圆柱形导电材料制成的中心导体，中心导体的厚度大于0.1mm且小于0.5mm; 围绕中心导体并由绝缘材料制成的电介质层; 围绕电介质层并由导电率大于97％且小于105％且厚度大于0.24mm且小于0.35mm的导电材料制成的外导体; 以及围绕外导体的外护套。 该同轴电缆即使在高频下也能稳定地传输信号。

公开(公告)号：US07882475B2

公开(公告)日：2011-02-01

申请号：US12181447

申请日：2008-07-29

申请人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia ,  Natarajan Viswanathan

发明人： Charles J. Alpert ,  Gi-Joon Nam ,  Haoxing Ren ,  Paul G. Villarrubia ,  Natarajan Viswanathan

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5072

摘要： A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects.

摘要翻译： 提出了一种强制定向布置程序的方法。 该方法包括：将多个对象从小区网表分配给分组; 基于箱子移动物体; 基于所述移动来计算所述多个对象中的每个对象的扩展力的大小; 基于物体的展开力的大小对物体进行分类; 基于指示基于位置拥塞的最高百分比，阈值力和阈值中的至少一个的阈值来选择排序对象的子集; 将所选择的物体的展开力调整为等于表示最小铺展力的预定值; 以及基于所选择的对象的调整的展开力确定所述对象的位置。