公开(公告)号：US20090193313A1

公开(公告)日：2009-07-30

申请号：US12149999

申请日：2008-05-12

申请人： Jun Jin Kong ,  Jae Hong Kim ,  Yong June Kim ,  Young Hwan Lee

发明人： Jun Jin Kong ,  Jae Hong Kim ,  Yong June Kim ,  Young Hwan Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/29 ,  H03M13/1102 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/23 ,  H03M13/2906 ,  H03M13/2957 ,  H03M13/2975 ,  H03M13/3738 ,  H03M13/6561

摘要： Provided are apparatuses for decoding a concatenated code and methods for the same that may improve the decoding speed of a concatenated code based on a likelihood value with respect to output from a plurality of decoders.A method of decoding a concatenated code may include: calculating a likelihood value of concatenated encoded received data; performing first decoding for the received data based on the calculated likelihood value to generate first decoded data; performing second decoding for the first decoded data to generate second decoded data; and determining whether to perform iterative decoding based on the second decoded data.According to example embodiments, it is possible to directly manage the quality of concatenated decoded data to thereby accurately determine whether to perform iterative decoding for concatenated encoded data. Also, it may be possible to quickly decode concatenated encoded received data.

摘要翻译： 提供了用于解码级联代码的装置及其方法，其可以基于相对于多个解码器的输出的似然值来提高级联代码的解码速度。 解码级联代码的方法可以包括：计算级联编码的接收数据的似然值; 基于所计算的似然值对接收到的数据执行第一解码以生成第一解码数据; 对所述第一解码数据执行第二解码以产生第二解码数据; 以及基于所述第二解码数据来确定是否执行迭代解码。 根据示例性实施例，可以直接管理级联解码数据的质量，从而准确地确定是否对级联编码数据执行迭代解码。 此外，可以快速解码连接编码的接收数据。

公开(公告)号：US08281217B2

公开(公告)日：2012-10-02

申请号：US12379746

申请日：2009-02-27

申请人： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong

发明人： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong

IPC分类号： G11C29/00

CPC分类号： H03M13/2903 ,  G06F11/1072 ,  H03M13/29 ,  H03M13/353

摘要： Memory devices and/or encoding/decoding methods are provided. A memory device may include: a memory cell array; an internal decoder configured to apply, to a first codeword read from the memory cell array, a first decoding scheme selected based on a characteristic of a first channel in which the first codeword is read to perform error control codes (ECC) decoding of the first codeword, and apply, to a second codeword read from the memory cell array, a second decoding scheme selected based on a characteristic of a second channel in which the second codeword is read to perform the ECC decoding of the second codeword; and an external decoder configured to apply an external decoding scheme to the ECC-decoded first codeword and the ECC-decoded second codeword to perform the ECC decoding of the first codeword and the second codeword.

摘要翻译： 提供存储器件和/或编码/解码方法。 存储器件可以包括：存储器单元阵列; 内部解码器，被配置为向从存储器单元阵列读取的第一代码字应用基于第一通道的特性选择的第一解码方案，其中读取第一代码字以执行第一代码字的错误控制代码（ECC）解码 代码字，并且应用于从存储单元阵列读取的第二码字，基于第二通道的特性选择的第二解码方案，其中读取第二码字以执行第二码字的ECC解码; 以及外部解码器，被配置为将外部解码方案应用于ECC解码的第一码字和ECC解码的第二码字，以执行第一码字和第二码字的ECC解码。

公开(公告)号：US20090241009A1

公开(公告)日：2009-09-24

申请号：US12232258

申请日：2008-09-12

申请人： Jun Jin Kong ,  Yong June Kim ,  Jae Hong Kim

发明人： Jun Jin Kong ,  Yong June Kim ,  Jae Hong Kim

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/03 ,  G06F11/1072 ,  H03M13/05

摘要： Encoding/decoding memory devices and methods thereof may be provided. A memory device according to example embodiments may include a memory cell array and a processor including at least one of a decoder and an encoder. The processor may be configured to adjust a redundant information rate of each channel, where each of the channels is a path of the memory cell array from which data is at least one of stored and read. The redundant information rate may be adjusted by generating at least one codeword based on information from a previous codeword. Therefore, example embodiments may reduce an error rate when data is read from and written to the memory device.

摘要翻译： 可以提供编码/解码存储器件及其方法。 根据示例实施例的存储器件可以包括存储单元阵列和包括解码器和编码器中的至少一个的处理器。 处理器可以被配置为调整每个通道的冗余信息速率，其中每个通道是存储单元阵列的路径，数据从存储单元阵列的至少一个存储和读取。 可以通过基于来自先前码字的信息生成至少一个码字来调整冗余信息速率。 因此，示例性实施例可以减少当数据从存储器件读取并写入存储器件时的错误率。

公开(公告)号：US20090241008A1

公开(公告)日：2009-09-24

申请号：US12379746

申请日：2009-02-27

申请人： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong

发明人： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong

IPC分类号： H03M13/29 ,  G06F11/10

CPC分类号： H03M13/2903 ,  G06F11/1072 ,  H03M13/29 ,  H03M13/353

摘要： Memory devices and/or encoding/decoding methods are provided. A memory device may include: a memory cell array; an internal decoder configured to apply, to a first codeword read from the memory cell array, a first decoding scheme selected based on a characteristic of a first channel in which the first codeword is read to perform error control codes (ECC) decoding of the first codeword, and apply, to a second codeword read from the memory cell array, a second decoding scheme selected based on a characteristic of a second channel in which the second codeword is read to perform the ECC decoding of the second codeword; and an external decoder configured to apply an external decoding scheme to the ECC-decoded first codeword and the ECC-decoded second codeword to perform the ECC decoding of the first codeword and the second codeword.

摘要翻译： 提供存储器件和/或编码/解码方法。 存储器件可以包括：存储器单元阵列; 内部解码器，被配置为向从存储器单元阵列读取的第一代码字应用基于第一通道的特性选择的第一解码方案，其中读取第一代码字以执行第一代码字的错误控制代码（ECC）解码 代码字，并且应用于从存储单元阵列读取的第二码字，基于第二通道的特性选择的第二解码方案，其中读取第二码字以执行第二码字的ECC解码; 以及外部解码器，被配置为将外部解码方案应用于ECC解码的第一码字和ECC解码的第二码字，以执行第一码字和第二码字的ECC解码。

公开(公告)号：US09158500B2

公开(公告)日：2015-10-13

申请号：US13537297

申请日：2012-06-29

申请人： Ki Jun Lee ,  Jun Jin Kong ,  Yong June Kim ,  Jae Hong Kim ,  Hong Rak Son ,  Jung Soo Chung ,  Seong Hyeong Choi

发明人： Ki Jun Lee ,  Jun Jin Kong ,  Yong June Kim ,  Jae Hong Kim ,  Hong Rak Son ,  Jung Soo Chung ,  Seong Hyeong Choi

IPC分类号： G06F7/58

CPC分类号： G06F7/584 ,  G06F2207/583

摘要： A data processing device which includes a conversion circuit and a pseudo random number generator including a series connection of plural shift registers. The conversion circuit receives a pseudo random number sequence from an output of one of the plural shift registers excluding a last shift register of the series connection, and converts first data to second data using the received pseudo random number sequence.

摘要翻译： 一种数据处理装置，包括转换电路和包括多个移位寄存器的串联连接的伪随机数发生器。 转换电路从除串行连接的最后一个移位寄存器之外的多个移位寄存器中的一个的输出接收伪随机数序列，并且使用接收到的伪随机数序列将第一数据转换为第二数据。

公开(公告)号：US08713411B2

公开(公告)日：2014-04-29

申请号：US12232258

申请日：2008-09-12

申请人： Jun Jin Kong ,  Yong June Kim ,  Jae Hong Kim

发明人： Jun Jin Kong ,  Yong June Kim ,  Jae Hong Kim

IPC分类号： H03M13/00

CPC分类号： H03M13/03 ,  G06F11/1072 ,  H03M13/05

摘要： Encoding/decoding memory devices and methods thereof may be provided. A memory device according to example embodiments may include a memory cell array and a processor including at least one of a decoder and an encoder. The processor may be configured to adjust a redundant information rate of each channel, where each of the channels is a path of the memory cell array from which data is at least one of stored and read. The redundant information rate may be adjusted by generating at least one codeword based on information from a previous codeword. Therefore, example embodiments may reduce an error rate when data is read from and written to the memory device.

摘要翻译： 可以提供编码/解码存储器件及其方法。 根据示例实施例的存储器件可以包括存储单元阵列和包括解码器和编码器中的至少一个的处理器。 处理器可以被配置为调整每个通道的冗余信息速率，其中每个通道是存储单元阵列的路径，数据从存储单元阵列的至少一个存储和读取。 可以通过基于来自先前码字的信息生成至少一个码字来调整冗余信息速率。 因此，示例性实施例可以减少当数据从存储器件读取并写入存储器件时的错误率。

公开(公告)号：US20100251077A1

公开(公告)日：2010-09-30

申请号：US12729285

申请日：2010-03-23

申请人： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

发明人： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Hong Rak Son

IPC分类号： G06F12/02 ,  H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1048

摘要： A storage device includes a controller unit and a memory cell array. The controller unit is for outputting data through a first data path or a second data path according to a property of externally supplied input data. The memory cell array includes a first memory and a second memory, and receives and stores the data from the controller unit output through the first and second data paths. The first memory has a different memory cell structure than the second memory.

摘要翻译： 存储装置包括控制器单元和存储单元阵列。 控制器单元用于根据外部提供的输入数据的属性通过第一数据路径或第二数据路径输出数据。 存储单元阵列包括第一存储器和第二存储器，并且通过第一和第二数据路径接收并存储来自控制器单元输出的数据。 第一存储器具有与第二存储器不同的存储单元结构。

公开(公告)号：US08413011B2

公开(公告)日：2013-04-02

申请号：US12651586

申请日：2010-01-04

申请人： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong

发明人： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong

IPC分类号： H03M13/00

CPC分类号： G06F11/1008 ,  H03M13/1105 ,  H03M13/1108

摘要： A 1-bit error correction method is provided. In the method, a variable node at which an error has occurred is detected based on a number of unsatisfied check nodes that do not satisfy a parity condition among check nodes connected to each of variable nodes and an error in a bit corresponding to the detected variable node is corrected.

摘要翻译： 提供1位纠错方法。 在该方法中，基于在连接到每个可变节点的校验节点中不满足奇偶校验条件的不满足校验节点的数量和对应于检测变量的位的错误来检测发生错误的变量节点 节点被更正。

公开(公告)号：US20090234792A1

公开(公告)日：2009-09-17

申请号：US12292539

申请日：2008-11-20

申请人： Jae Hong Kim ,  Heeseok Eun ,  Yong June Kim ,  Jun Jin Kong ,  Seung-Hwan Song

发明人： Jae Hong Kim ,  Heeseok Eun ,  Yong June Kim ,  Jun Jin Kong ,  Seung-Hwan Song

IPC分类号： G06N5/00

CPC分类号： G06N99/005

摘要： Disclosed are a memory device and a data decision method. The memory device may include a memory cell array, and a decision unit configured to read first data from the memory cell array via a first channel, perform at least one of a hard and soft decision on the first data using a first number of decision levels set based on characteristics of the first channel, read second data from the memory cell array via a second channel, and perform a soft decision on the second data using a second number of decision levels set based on characteristics of the second channel.

摘要翻译： 公开了一种存储器件和数据判定方法。 存储器装置可以包括存储单元阵列，以及判定单元，被配置为经由第一通道从存储单元阵列读取第一数据，使用第一数量的判定级别对第一数据执行硬判决和软判决中的至少一个 基于第一信道的特性设置，经由第二信道从存储器单元阵列读取第二数据，并且使用基于第二信道的特性设置的第二数量的判定级来对第二数据执行软判决。

公开(公告)号：US20110249495A1

公开(公告)日：2011-10-13

申请号：US13071727

申请日：2011-03-25

申请人： Kyoung Lae Cho ,  Hyuck-Sun Kwon ,  Jun Jin Kong

发明人： Kyoung Lae Cho ,  Hyuck-Sun Kwon ,  Jun Jin Kong

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/3454

摘要： A non-volatile memory device is provided. The non-volatile memory device includes a memory cell array including a plurality of multi-level cells each storing data corresponding to one of a plurality of states of a first group of states, and a control circuit. The control circuit configured to program data corresponding to one of the plurality of states in a first multi-level cell according to a first verify voltage level of a first group of verify voltage levels, and to control the first multi-level cell to be re-programmed to one of a plurality of states of a second group of states according to a first verify voltage level of a second group of verify voltage levels. Each voltage level of the second group of verify voltage levels has a higher level than the verify voltage levels of the first group of verify voltage levels. One of the plurality of states of the second group of states includes at least one of the plurality of states of the first group of states.

摘要翻译： 提供了一种非易失性存储器件。 非易失性存储器件包括存储单元阵列，其包括多个多电平单元，每个多电平单元存储与第一组状态的多个状态中的一个对应的数据，以及控制电路。 控制电路被配置为根据第一组验证电压电平的第一验证电压电平对第一多电平单元中的多个状态中的一个状态进行编程的数据，并且控制第一多电平单元被重新 根据第二验证电压电平组的第一验证电压电平编程为第二组状态的多个状态中的一个状态。 第二组验证电压电平的每个电压电平具有比第一组验证电压电平的验证电压电平更高的电平。 第二组状态的多个状态之一包括第一组状态的多个状态中的至少一个状态。