公开(公告)号：US5777679A

公开(公告)日：1998-07-07

申请号：US616327

申请日：1996-03-15

申请人： Dennis Phillip Cheney ,  David Allen Hrusecky ,  Mihailo M. Stojancic

发明人： Dennis Phillip Cheney ,  David Allen Hrusecky ,  Mihailo M. Stojancic

IPC分类号： H04N5/92 ,  G06T9/00 ,  G09G5/39 ,  H03M7/36 ,  H04N5/44 ,  H04N7/32 ,  H04N21/4143 ,  H04N21/4402 ,  H04N21/443 ,  H04N7/12

CPC分类号： H04N5/4401 ,  G06T9/007 ,  G09G5/39 ,  H04N19/436 ,  H04N19/44 ,  H04N19/59 ,  H04N19/80 ,  H04N21/4143 ,  H04N21/440272 ,  H04N21/4435 ,  G09G2340/02

摘要： A digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals with accurate expansion for various aspect ratios. This is accomplished through convolution multiplication carried out in 4-tuple parallel with 4-2 counters through a folding serial adder which creates a convolution sum of pixels of the motion compensated data stream to thereby expand the output video display to the desired aspect ratio.

摘要翻译： 一种数字信号解码器系统，用于接收压缩编码的数字化视频信号，并以各种宽高比的精确扩展发送解压缩的解码数字视频信号。 这是通过卷积乘法实现的，其通过折叠串行加法器与4-2计数器并行的4元组进行，其产生运动补偿数据流的像素的卷积和，从而将输出视频显示扩展到期望的宽高比。

公开(公告)号：US08542744B2

公开(公告)日：2013-09-24

申请号：US11737175

申请日：2007-04-19

申请人： Mihailo M. Stojancic ,  Gerald George Pechanek

发明人： Mihailo M. Stojancic ,  Gerald George Pechanek

IPC分类号： H04N7/12 ,  H04N9/64 ,  H04N5/222

CPC分类号： H04N19/80 ,  H04N19/42 ,  H04N19/436 ,  H04N19/59

摘要： Apparatus and methods for scalable block pixel filtering are described. A block filtering instruction is issued to a processing element (PE) to initiate block pixel filtering hardware by causing at least one command and at least one parameter be sent to a command and control function associated with the PE. A block of pixels is fetched from a PE local memory to be stored in a register file of a hardware assist module. A sub-block of pixels is processed to generate sub-block parameters and the block of pixels is filtered in a horizontal/vertical edge filtering computation pipeline using the sub-block parameters.

公开(公告)号：US08385644B2

公开(公告)日：2013-02-26

申请号：US12491896

申请日：2009-06-25

申请人： Mihailo M. Stojancic

发明人： Mihailo M. Stojancic

IPC分类号： G06K9/00

CPC分类号： G06F17/30799 ,  G06K9/00744 ,  H04N5/147 ,  H04N21/835

摘要： Video sequence processing with various filtering rules is applied to extract dominant spatial features and generate unique set of signatures describing video content. Accurate active regions are determined for each video sequence frame. Subsequently, a video sequence is structured by tracking statistical changes in the content of a succession of video frames, and suitable frames are selected for further spatial processing. Selected video frames are processed for feature extraction and description, and compact representative signatures are generated, resulting in an efficient video database formation and search.

摘要翻译： 应用具有各种过滤规则的视频序列处理来提取主要空间特征并生成描述视频内容的唯一签名集合。 确定每个视频序列帧的精确有效区域。 随后，通过跟踪一系列视频帧的内容的统计变化来构造视频序列，并且选择合适的帧用于进一步的空间处理。 处理所选择的视频帧以进行特征提取和描述，并且生成紧凑的代表性签名，从而形成和搜索高效的视频数据。

公开(公告)号：US08385419B2

公开(公告)日：2013-02-26

申请号：US11736670

申请日：2007-04-18

申请人： Mihailo M. Stojancic ,  Gerald George Pechanek

发明人： Mihailo M. Stojancic ,  Gerald George Pechanek

IPC分类号： H04N7/12

CPC分类号： H04N19/433 ,  H04N19/186 ,  H04N19/43 ,  H04N19/436 ,  H04N19/523 ,  H04N19/57 ,  H04N19/61

摘要： Various approaches for motion search refinement in a processing element are discussed. A k/2+L+k/2 register stores an expanded row of an L×L macro block. A k-tap filter horizontally interpolates over the expanded row generating horizontal interpolation, results. A transpose storage unit stores the interpolated results generated by the k-tap filter for k/2+L+k/2 entries, wherein rows or columns of data may be read out of the transpose storage unit in pipelined register stages. A k-tap filter vertically interpolates over the pipelined register stages generating vertical interpolation results.

摘要翻译： 讨论了处理元件中运动搜索细化的各种方法。 A k / 2 + L + k / 2寄存器存储L×L宏块的扩展行。 k抽头滤波器在扩展行上水平插值，产生水平插值，结果。 转置存储单元存储由k抽头滤波器为k / 2 + L + k / 2个条目生成的内插结果，其中数据行或列可以在流水线寄存器级中从转置存储单元中读出。 k抽头滤波器垂直内插在流水线寄存器级上，产生垂直插值结果。

公开(公告)号：US07971036B2

公开(公告)日：2011-06-28

申请号：US11736788

申请日：2007-04-18

申请人： Gerald George Pechanek ,  Mihailo M. Stojancic

发明人： Gerald George Pechanek ,  Mihailo M. Stojancic

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F15/80 ,  G06F9/30036 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3851 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3891

摘要： A multi-node video signal processor (VSPN) is describes that tightly couples multiple multi-cycle state machines (hardware assist units) to each processor and each memory in each node of an N node scalable array processor. VSPN memory hardware assist instructions are used to initiate multi-cycle state machine functions, to pass parameters to the multi-cycle state machines, to fetch operands from a node's memory, and to control the transfer of results from the multi-cycle state machines.

摘要翻译： 描述了一种多节点视频信号处理器（VSPN），它将多个多周期状态机（硬件辅助单元）紧密耦合到N个节点可扩展阵列处理器的每个节点的每个处理器和每个存储器。 VSPN存储器硬件辅助指令用于启动多周期状态机功能，将参数传递到多周期状态机，从节点的存储器获取操作数，并控制多循环状态机的结果传输。

公开(公告)号：US07730280B2

公开(公告)日：2010-06-01

申请号：US11736814

申请日：2007-04-18

申请人： Gerald George Pechanek ,  Edwin Franklin Barry ,  Mihailo M. Stojancic

发明人： Gerald George Pechanek ,  Edwin Franklin Barry ,  Mihailo M. Stojancic

IPC分类号： G06F15/76

CPC分类号： G06F9/3009 ,  G06F9/32 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889 ,  G06F15/8007

摘要： A control processor is used for fetching and distributing single instruction multiple data (SIMD) instructions to a plurality of processing elements (PEs). One of the SIMD instructions is a thread start (Tstart) instruction, which causes the control processor to pause its instruction fetching. A local PE instruction memory (PE Imem) is associated with each PE and contains local PE instructions for execution on the local PE. Local PE Imem fetch, decode, and execute logic are associated with each PE. Instruction path selection logic in each PE is used to select between control processor distributed instructions and local PE instructions fetched from the local PE Imem. Each PE is also initialized to receive control processor distributed instructions. In addition, local hold generation logic is associated with each PE. A PE receiving a Tstart instruction causes the instruction path selection logic to switch to fetch local PE Imem instructions.

摘要翻译： 控制处理器用于将单指令多数据（SIMD）指令提取并分发给多个处理元件（PE）。 SIMD指令之一是线程启动（Tstart）指令，它使控制处理器暂停其指令提取。 本地PE指令存储器（PE Imem）与每个PE相关联，并且包含用于在本地PE上执行的本地PE指令。 本地PE Imem提取，解码和执行逻辑与每个PE相关联。 每个PE中的指令路径选择逻辑用于在控制处理器分布式指令和从本地PE Imem获取的本地PE指令之间进行选择。 每个PE也被初始化以接收控制处理器分布式指令。 此外，本地保持生成逻辑与每个PE相关联。 接收Tstart指令的PE使指令路径选择逻辑切换到获取本地PE Imem指令。

公开(公告)号：US20100007797A1

公开(公告)日：2010-01-14

申请号：US12491896

申请日：2009-06-25

申请人： Mihailo M. Stojancic

发明人： Mihailo M. Stojancic

IPC分类号： H04N5/00

CPC分类号： G06F17/30799 ,  G06K9/00744 ,  H04N5/147 ,  H04N21/835

摘要： Video sequence processing with various filtering rules is applied to extract dominant spatial features and generate unique set of signatures describing video content. Accurate active regions are determined for each video sequence frame. Subsequently, a video sequence is structured by tracking statistical changes in the content of a succession of video frames, and suitable frames are selected for further spatial processing. Selected video frames are processed for feature extraction and description, and compact representative signatures are generated, resulting in an efficient video database formation and search.

摘要翻译： 应用具有各种过滤规则的视频序列处理来提取主要空间特征并生成描述视频内容的唯一签名集合。 确定每个视频序列帧的精确有效区域。 随后，通过跟踪一系列视频帧的内容的统计变化来构造视频序列，并且选择合适的帧用于进一步的空间处理。 处理所选择的视频帧以进行特征提取和描述，并且生成紧凑的代表性签名，从而形成和搜索高效的视频数据。

公开(公告)号：US20080046685A1

公开(公告)日：2008-02-21

申请号：US11736814

申请日：2007-04-18

申请人： Gerald George Pechanek ,  Edwin Franklin Barry ,  Mihailo M. Stojancic

发明人： Gerald George Pechanek ,  Edwin Franklin Barry ,  Mihailo M. Stojancic

IPC分类号： G06F15/00

CPC分类号： G06F9/3009 ,  G06F9/32 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889 ,  G06F15/8007

摘要： A control processor is used for fetching and distributing single instruction multiple data (SIMD) instructions to a plurality of processing elements (PEs). One of the SIMD instructions is a thread start (Tstart) instruction, which causes the control processor to pause its instruction fetching. A local PE instruction memory (PE Imem) is associated with each PE and contains local PE instructions for execution on the local PE. Local PE Imem fetch, decode, and execute logic are associated with each PE. Instruction path selection logic in each PE is used to select between control processor distributed instructions and local PE instructions fetched from the local PE Imem. Each PE is also initialized to receive control processor distributed instructions. In addition, local hold generation logic is associated with each PE. A PE receiving a Tstart instruction causes the instruction path selection logic to switch to fetch local PE Imem instructions.

摘要翻译： 控制处理器用于将单指令多数据（SIMD）指令提取并分发给多个处理元件（PE）。 SIMD指令之一是线程启动（Tstart）指令，它使控制处理器暂停其指令提取。 本地PE指令存储器（PE Imem）与每个PE相关联，并且包含用于在本地PE上执行的本地PE指令。 本地PE Imem提取，解码和执行逻辑与每个PE相关联。 每个PE中的指令路径选择逻辑用于在控制处理器分布式指令和从本地PE Imem获取的本地PE指令之间进行选择。 每个PE也被初始化以接收控制处理器分布式指令。 此外，本地保持生成逻辑与每个PE相关联。 接收Tstart指令的PE使指令路径选择逻辑切换到获取本地PE Imem指令。

公开(公告)号：US20080040411A1

公开(公告)日：2008-02-14

申请号：US11736670

申请日：2007-04-18

申请人： Mihailo M. Stojancic ,  Gerald George Pechanek

发明人： Mihailo M. Stojancic ,  Gerald George Pechanek

IPC分类号： G06F7/38

CPC分类号： H04N19/433 ,  H04N19/186 ,  H04N19/43 ,  H04N19/436 ,  H04N19/523 ,  H04N19/57 ,  H04N19/61

摘要： Various approaches for motion search refinement in a processing element are discussed. A k/2+L+k/2 register stores an expanded row of an L×L macro block. A k-tap filter horizontally interpolates over the expanded row generating horizontal interpolation, results. A transpose storage unit stores the interpolated results generated by the k-tap filter for k/2+L+k/2 entries, wherein rows or columns of data may be read out of the transpose storage unit in pipelined register stages. A k-tap filter vertically interpolates over the pipelined register stages generating vertical interpolation results.

摘要翻译： 讨论了处理元件中运动搜索细化的各种方法。 A k / 2 + L + k / 2寄存器存储LxL宏块的扩展行。 k抽头滤波器在扩展行上水平内插，产生水平插值，结果。 转置存储单元存储由k抽头滤波器为k / 2 + L + k / 2个条目生成的内插结果，其中数据行或列可以在流水线寄存器级中从转置存储单元中读出。 k抽头滤波器垂直内插在流水线寄存器级上，产生垂直插值结果。

公开(公告)号：US20080037647A1

公开(公告)日：2008-02-14

申请号：US11736849

申请日：2007-04-18

申请人： Mihailo M. Stojancic ,  Gerald George Pechanek

发明人： Mihailo M. Stojancic ,  Gerald George Pechanek

IPC分类号： H04N11/04 ,  H04N7/12

CPC分类号： H04N19/523 ,  H04N19/43 ,  H04N19/436

摘要： An apparatus and a method for quarter-pel motion compensated search are described in the context of an array processor with tightly coupled, multi-cycle hardware assist attached to each node. A quarter-pel motion compensated search (QPMCS) instruction initiates the quarter-pel motion compensated search pipeline operation. An instruction decode and instruction operation control unit generates a starting address for a 4×4 block of a current macro block search operation indicating where to fetch the pel values. An interpolation unit determines at least eight neighboring quarter-pels per pipeline stage based on the 4×4 block of pel values. An absolute value of difference function computes the absolute value of difference values between a current macro block pel and the at least eight neighboring quarter-pels per pipeline stage. An accumulator accumulates at least eight summation values for the 4×4 block at quarter-pel positions per pipeline stage.

摘要翻译： 在具有连接到每个节点的紧密耦合的多周期硬件辅助的阵列处理器的上下文中描述了用于四分之一像素运动补偿搜索的装置和方法。 四分之一像素运动补偿搜索（QPMCS）指令启动四分之一像素运动补偿搜索管道操作。 指令解码和指令操作控制单元产生指示在哪里获取像素值的当前宏块搜索操作的4×4块的起始地址。 插值单元基于像素值的4×4块来确定每个流水线阶段的至少八个相邻四分之一像素。 差分函数的绝对值计算当前宏块和每个流水线阶段至少八个相邻四分之一像素之间的差值的绝对值。 累加器在每个流水线阶段的四分之一像素位置累积至少八个求和值。