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公开(公告)号：US5777679A
公开(公告)日：1998-07-07
申请号：US616327
申请日：1996-03-15
IPC分类号： H04N5/92 , G06T9/00 , G09G5/39 , H03M7/36 , H04N5/44 , H04N7/32 , H04N21/4143 , H04N21/4402 , H04N21/443 , H04N7/12
CPC分类号： H04N5/4401 , G06T9/007 , G09G5/39 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/80 , H04N21/4143 , H04N21/440272 , H04N21/4435 , G09G2340/02
摘要： A digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals with accurate expansion for various aspect ratios. This is accomplished through convolution multiplication carried out in 4-tuple parallel with 4-2 counters through a folding serial adder which creates a convolution sum of pixels of the motion compensated data stream to thereby expand the output video display to the desired aspect ratio.
摘要翻译： 一种数字信号解码器系统，用于接收压缩编码的数字化视频信号，并以各种宽高比的精确扩展发送解压缩的解码数字视频信号。 这是通过卷积乘法实现的，其通过折叠串行加法器与4-2计数器并行的4元组进行，其产生运动补偿数据流的像素的卷积和，从而将输出视频显示扩展到期望的宽高比。
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公开(公告)号：US5668599A
公开(公告)日：1997-09-16
申请号：US618660
申请日：1996-03-19
申请人： Dennis Phillip Cheney , Mark Louis Ciacelli , Steven Bradford Herndon , John David Myers , Chuck Hong Ngai
发明人： Dennis Phillip Cheney , Mark Louis Ciacelli , Steven Bradford Herndon , John David Myers , Chuck Hong Ngai
CPC分类号： H04N5/4401 , H04N19/423 , H04N19/427 , H04N19/61 , H04N21/4305 , H04N21/44004 , H04N5/907
摘要： Disclosed is a digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals. This is accomplished with a minimum of DRAM demand through the use of a Spill Buffer.
摘要翻译： 公开了一种用于接收压缩编码的数字化视频信号并发送解压缩解码的数字视频信号的数字信号解码器系统。 这是通过使用溢出缓冲区的DRAM需求来实现的。
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公开(公告)号：US5929911A
公开(公告)日：1999-07-27
申请号：US958632
申请日：1997-10-27
CPC分类号： H04N9/64 , H04N19/186 , H04N19/423 , H04N19/427 , H04N19/428 , H04N19/433 , H04N19/577 , H04N19/59 , H04N19/61 , H04N19/80 , H04N21/4435 , H04N5/4401 , H04N7/0122 , H04N11/20
摘要： A digital signal decoder system is provided for receiving digital video signals and processing them while reducing the external memory requirements for frame buffer storage for an MPEG-2 decoder through decimation. The system includes a motion compensation unit for processing macroblock data. The decoder portion of the decimation unit intercepts and processes the data after it has been processed by the motion compensation unit. The data is then stored in the decimate buffer before passing on to the memory control unit. From here the data is routed to the display portion of the decimation unit for further processing. At this point the data is stored in the video buffer where it then passes on to the expansion filter and then to the display. As the video data is routed through the system, it could be decimated, interpolated, reduced, expanded, or any combination of these. The decoder controller controls and synchronizes the system operation. The final result is a system for decoding digital video signals while reducing the external memory requirements. This decoding system can be used to provide features that are desirable for MPEG-2 playback. These include display format conversion to letterbox, and display format conversion to 3/4 small picture size with additional storage allocation for on screen graphics.
摘要翻译： 提供数字信号解码器系统用于接收数字视频信号并进行处理，同时通过抽取减少MPEG-2解码器的帧缓冲存储器的外部存储器要求。 该系统包括用于处理宏块数据的运动补偿单元。 抽取单元的解码器部分在由运动补偿单元处理之后截取并处理数据。 然后将数据存储在抽取缓冲器中，然后再传送到存储器控制单元。 从这里，数据被路由到抽取单元的显示部分以进一步处理。 此时，数据被存储在视频缓冲器中，然后传送到扩展过滤器，然后传送到显示器。 当视频数据通过系统路由时，可以对其进行抽取，内插，缩小，扩展或者任意组合。 解码器控制器控制并同步系统操作。 最终的结果是在减少外部存储器要求的同时解码数字视频信号的系统。 该解码系统可用于提供MPEG-2播放所需的特征。 这些包括显示格式转换为letterbox，并显示格式转换为+ E，fra 3/4 + EE小图片大小，带有额外的屏幕图形存储分配。
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